cpu-cache

问题 Can a lower level cache have higher associativity and still hold inclusion? Suppose we have 2-level of cache.(L1 being nearest to CPU and L2 being nearest to main memory) L1 cache is 2-way set associative with 4 sets and let's say L2 cache is direct mapped with 16 cache lines and assume that both caches have same block size. Then I think it will follow inclusion property even though L1(lower level) has higher associativity than L2 (upper level). As per my understanding, lower level cache can

问题 I have been reading about the four ways a cache can be addressed: Physically Indexed Physically Tagged (PIPT) Physically Indexed Virtually Tagged (PIVT) Virtually Indexed Physically Tagged (VIPT) Virtually Indexed Virtually Tagged (VIVT) Which of the following caches would suffer from the synonym and homonym issues? I know that the VIVT would suffer from these issues and PIPT won't. But what about PIVT and VIPT? 回答1: Since synonyms occur when different virtual addresses map to the same

问题 Is there any way to read the CPU cache contents? Architecture is for ARM. I m invalidating a range of addresses and then want to make sure whether it is invalidated or not. Although I can do read and write of the range of addresses with and without invalidating and checking the invalidation, I want to know whether it is possible to read the cache contents Thanks!! 回答1: ARM9 provides cache manipulation and test registers that allow you to examine the state of the cache. Here's a reasonable

问题 I am trying to use clflush to manually evicts a cache line in order to determine cache and line sizes. I didn't find any guide on how to use that instruction. All I see, are some codes that use higher level functions for that purpose. There is a kernel function void clflush_cache_range(void *vaddr, unsigned int size) , but still I don't know what to include in my code and how to use that. I don't know what is the size in that function. More than that, how can I be sure that the line is

问题 I've been reading about SOA and I wanted to try an implement it in a system that I am building up. I am writing some simple C struct to do some tests but I am a bit confused, right now I have 3 different struct for a vec3 . I will show them below and then go into further details about the question. struct vec3 { size_t x, y, z; }; struct vec3_a { size_t pos[3]; }; struct vec3_b { size_t* x; size_t* y; size_t* z; }; struct vec3 vec3(size_t x, size_t y, size_t z) { struct vec3 v; v.x = x; v.y =

问题 Under the total store order(TSO) memory consistency model, a x86 cpu will have a write buffer to buffer write requests and can serve reordered read requests from the write buffer. And it says that the write requests in the write buffer will exit and be issued toward cache hierarchy in FIFO order, which is the same as program order. I am curious about: To serve the write requests issued from the write buffer, does L1 cache controller handle the write requests, finish the cache coherence of the

问题 Consider this function in C++: void foo(uint32_t *a1, uint32_t *a2, uint32_t *b1, uint32_t *b2, uint32_t *o) { while (b1 != b2) { // assert(0 <= *b1 && *b1 < a2 - a1) *o++ = a1[*b1++]; } } Its purpose should be clear enough. Unfortunately, b1 contains random data and trash the cache, making foo the bottleneck of my program. Is there anyway I can optimize it? This is an SSCCE that should resemble my actual code: #include <iostream> #include <chrono> #include <algorithm> #include <numeric>

问题 I am reading about different prefetcher available in Intel Core i7 system. I have performed experiments to understand when these prefetchers are invoked. These are my findings L1 IP prefetchers starts prefetching after 3 cache misses. It only prefetch on cache hit. L2 Adjacent line prefetcher starts prefetching after 1st cache miss and prefetch on cache miss. L2 H/W (stride) prefetcher starts prefetching after 1st cache miss and prefetch on cache hit. I am not able to understand the behavior

问题 I'm trying to figure out how to calculate the miss rate of an array. I have the answer, but I'm not understanding how the answer was arrived at. I have the following code: int C[N1][N2]; int A[N1][N3]; int B[N3][N2]; initialize_arrays(A, B, C, N1, N2, N3); for(i=0; i<N1; ++i) for(j=0; j<N2; ++j) for(k=0; k<N3, ++k) C[i][j] += A[i][k] * B[k][j]; I also have the following info: N1=N2=N3=2048 (what does this mean??). The processor has an L1 data cache of 32kB with line size of 64B (no L2 cache).

问题 Does anyone know which type of CPU cache behaviour or policy (e.g. uncacheable write-combining) is assigned to memory mapped file-backed regions on modern x86 systems? Is there any way to detect which is the case, and possibly override the default behaviour? Windows and Linux are the main operating systems of interest. (Editor's note: the question was previously phrased as memory mapped I/O, but that phrase has a different specific technical meaning, especially when talking about CPU caches.