cpu-cache

来源： https://stackoverflow.com/questions/14259088/cache-addressing-length-of-index-block-offset-byte-offset-tag

来源： https://stackoverflow.com/questions/62221034/can-you-directly-access-the-cache-using-assembly

来源： https://stackoverflow.com/questions/54072810/is-mov-r64-m64-one-cycle-or-two-cycle-latency

来源： https://stackoverflow.com/questions/54072810/is-mov-r64-m64-one-cycle-or-two-cycle-latency

来源： https://stackoverflow.com/questions/54072810/is-mov-r64-m64-one-cycle-or-two-cycle-latency

问题 I have a little question about the algorithm LRU. If you have a cache with four blocs , how many bits do you need to implement this algorithm ? 回答1: There is a good slide-deck at http://www.powershow.com/view/95163-NzkyO/4_4_Page_replacement_algorithms_powerpoint_ppt_presentation that talks about various page replacement schemes. It also explains the LRU implementation using mxm matrix really well. 回答2: Assuming you mean a 4-way set-associative cache: A "perfect" LRU would essentially be

问题 I assume simple spinlock that does not go to OS waiting for the purposes of this question. I see that simple spinlock is often implemented using lock xchg or lock bts instead of lock cmpxchg . But doesn't cmpxchg avoid writing the value if the expectation does not match? So aren't failed attempts cheaper with cmpxchg ? Or does cmpxchg write data and invalidate cache line of other cores even on failure? This question is similar to What specifically marks an x86 cache line as dirty - any write,

问题 I am somewhat confused with what how cache coherence systems function in modern multi core CPU. I have seen that snooping based protocols like MESIF/MOESI snooping based protocols have been used in Intel and AMD processors, on the other hand directory based protocols seem to be a lot more efficient with multiple core as they don't broadcast but send messages to specific nodes. What is the modern cache coherence solution in AMD or Intel processors, is it snooping based protocols like MOESI and

问题 I'm a little confused by the meaning of "Aliasing" between CPU-cache and Physical address . First I found It's definition on Wikipedia : However, VIVT suffers from aliasing problems, where several different virtual addresses may refer to the same physical address . Another problem is homonyms, where the same virtual address maps to several different physical addresses. but after a while I saw a different definition on a presentation( ppt ) of DAC'05: "Energy-Efficient Physically Tagged Caches

问题 I was doing a question on Computer Architecture and in it it was mentioned that the cache is a split cache, and no hazard what does this exactly means? 回答1: Introduction A split cache is a cache that consists of two physically separate parts, where one part, called the instruction cache, is dedicated for holding instructions and the other, called the data cache, is dedicated for holding data (i.e., instruction memory operands). Both of the instruction cache and data cache are logically