cpu-cache

问题 I\'m writing a small program in C, and I want to measure it\'s performance. I want to see how much time do it run in the processor and how many cache hit+misses has it made. Information about context switches and memory usage would be nice to have too. The program takes less than a second to execute. I like the information of /proc/[pid]/stat, but I don\'t know how to see it after the program has died/been killed. Any ideas? EDIT: I think Valgrind adds a lot of overhead. That\'s why I wanted

问题 Can some of the load instructions be never globally visible due to store load forwarding ? To put it another way, if a load instruction gets its value from the store buffer, it never has to read from the cache. As it is generally stated that a load is globally visible when it reads from the L1D cache, the ones that do not read from the L1D should make it globally invisible. 回答1: The concept of global visibility for loads is tricky, because a load doesn't modify the global state of memory, and

问题 This could sound like a subjective question, but what I am looking for are specific instances, which you could have encountered related to this. How to make code, cache effective/cache friendly (more cache hits, as few cache misses as possible)? From both perspectives, data cache & program cache (instruction cache), i.e. what things in one\'s code, related to data structures and code constructs, should one take care of to make it cache effective. Are there any particular data structures one

问题 I am interested in forcing a CPU cache flush in Windows (for benchmarking reasons, I want to emulate starting with no data in CPU cache), preferably a basic C implementation or Win32 call. Is there a known way to do this with a system call or even something as sneaky as doing say a large memcpy ? Intel i686 platform (P4 and up is okay as well). 回答1: Fortunately, there is more than one way to explicitly flush the caches. The instruction "wbinvd" writes back modified cache content and marks the

问题 When executing a series of _mm_stream_load_si128() calls ( MOVNTDQA ) from consecutive memory locations, will the hardware pre-fetcher still kick-in, or should I use explicit software prefetching (with NTA hint) in order to obtain the benefits of prefetching while still avoiding cache pollution? The reason I ask this is because their objectives seem contradictory to me. A streaming load will fetch data bypassing the cache, while the pre-fetcher attempts to proactively fetch data into the

问题 This question already has an answer here: Why does the order of the loops affect performance when iterating over a 2D array? 7 answers Which of the following orderings of nested loops to iterate over a 2D array is more efficient in terms of time (cache performance)? Why? int a[100][100]; for(i=0; i<100; i++) { for(j=0; j<100; j++) { a[i][j] = 10; } } or for(i=0; i<100; i++) { for(j=0; j<100; j++) { a[j][i] = 10; } } 回答1: The first method is slightly better, as the cells being assigned to lays

问题 I have learned about different cache mapping technique like direct mapping,associate mapping and set associative mapping technique and also learned the trade-offs. But I am curious what is used in intel core i7 or AMD processor nowadays. And how the techniques are evolved. And what are things that needs to be improved? 回答1: Direct-mapped caches are basically never used in modern high-performance CPUs . The power savings are outweighed by the large advantage in hit rate for a set-associative

问题 Why is the size of L1 cache smaller than that of the L2 cache in most of the processors ? 回答1: There are different reasons for that. L2 exists in the system to speedup the case where there is a L1 cache miss. If the size of L1 was the same or bigger than the size of L2, then L2 could not accomodate for more cache lines than L1, and would not be able to deal with L1 cache misses. From the design/cost perspective, L1 cache is bound to the processor and faster than L2. The whole idea of caches

问题 Can anyone give me the approximate time (in nanoseconds) to access L1, L2 and L3 caches, as well as main memory on Intel i7 processors? While this isn\'t specifically a programming question, knowing these kinds of speed details is neccessary for some low-latency programming challenges. 回答1: Here is a Performance Analysis Guide for the i7 and Xeon range of processors. I should stress, this has what you need and more (for example, check page 22 for some timings & cycles for example).

问题 Below are two programs that are almost identical except that I switched the i and j variables around. They both run in different amounts of time. Could someone explain why this happens? Version 1 #include <stdio.h> #include <stdlib.h> main () { int i,j; static int x[4000][4000]; for (i = 0; i < 4000; i++) { for (j = 0; j < 4000; j++) { x[j][i] = i + j; } } } Version 2 #include <stdio.h> #include <stdlib.h> main () { int i,j; static int x[4000][4000]; for (j = 0; j < 4000; j++) { for (i = 0; i