cpu-cache

The other week, I wrote a little thread class and a one-way message pipe to allow communication between threads (two pipes per thread, obviously, for bidirectional communication). Everything worked fine on my Athlon 64 X2, but I was wondering if I'd run into any problems if both threads were looking at the same variable and the local cached value for this variable on each core was out of sync. I know the volatile keyword will force a variable to refresh from memory, but is there a way on multicore x86 processors to force the caches of all cores to synchronize? Is this something I need to worry

I got this program from this link ( https://gist.github.com/jiewmeng/3787223).I have been searching the web with the idea of gaining a better understanding of processor caches (L1 and L2).I want to be able to write a program that would enable me to guess the size of L1 and L2 cache on my new Laptop.(just for learning purpose.I know I could check the spec.) #include <stdio.h> #include <stdlib.h> #include <time.h> #define KB 1024 #define MB 1024 * 1024 int main() { unsigned int steps = 256 * 1024 * 1024; static int arr[4 * 1024 * 1024]; int lengthMod; unsigned int i; double timeTaken; clock_t

I'm writing a small program in C, and I want to measure it's performance. I want to see how much time do it run in the processor and how many cache hit+misses has it made. Information about context switches and memory usage would be nice to have too. The program takes less than a second to execute. I like the information of /proc/[pid]/stat, but I don't know how to see it after the program has died/been killed. Any ideas? EDIT: I think Valgrind adds a lot of overhead. That's why I wanted a simple tool, like /proc/[pid]/stat, that is always there. Use perf : perf stat ./yourapp See the kernel

Can some of the load instructions be never globally visible due to store load forwarding ? To put it another way, if a load instruction gets its value from the store buffer, it never has to read from the cache. As it is generally stated that a load is globally visible when it reads from the L1D cache, the ones that do not read from the L1D should make it globally invisible. The concept of global visibility for loads is tricky, because a load doesn't modify the global state of memory, and other threads can't directly observe it. But once the dust settles after out-of-order / speculative

This could sound like a subjective question, but what I am looking for are specific instances, which you could have encountered related to this. How to make code, cache effective/cache friendly (more cache hits, as few cache misses as possible)? From both perspectives, data cache & program cache (instruction cache), i.e. what things in one's code, related to data structures and code constructs, should one take care of to make it cache effective. Are there any particular data structures one must use/avoid, or is there a particular way of accessing the members of that structure etc... to make