cpu-cache

I am having problem in understanding locality of reference. Can anyone please help me out in understanding what it means and what is, Spatial Locality of reference Temporal Locality of reference This would not matter if your computer was filled with super-fast memory. But unfortunately that's not the case and computer-memory looks something like this 1 : +----------+ | CPU | <<-- Our beloved CPU, superfast and always hungry for more data. +----------+ |L1 - Cache| <<-- works at 100% of CPU speed (fast) +----------+ |L2 - Cache| <<-- works at 25% of CPU speed (medium) +----+-----+ | | <<-- This

I remember assuming that an L1 cache hit is 1 cycle (i.e. identical to register access time) in my architecture class, but is that actually true on modern x86 processors? How many cycles does an L1 cache hit take? How does it compare to register access? paulsm4 Here's a great article on the subject: http://arstechnica.com/gadgets/reviews/2002/07/caching.ars/1 To answer your question - yes, a cache hit has approximately the same cost as a register access. And of course a cache miss is quite costly ;) PS: The specifics will vary, but this link has some good ballpark figures: Approximate cost to

Capacity miss occurs because blocks are being discarded from cache because cache cannot contain all blocks needed for program execution (program working set is much larger than cache capacity). Conflict miss occurs in the case of set associative or direct mapped block placement strategies, conflict misses occur when several blocks are mapped to the same set or block frame; also called collision misses or interference misses. Are they actually very closely related? For example, if all the cache lines are filled and we have a read request for memory B, for which we have to evict memory A. So

I am trying to understand how CPU cache is operating. Lets say we have this configuration (as an example). Cache size 1024 bytes Cache line 32 bytes 1024/32 = 32 cache lines all together. Singel cache line can store 32/4 = 8 ints. 1) According to these configuration length of tag should be 32-5=27 bits, and size of index 5 bits (2^5 = 32 addresses for each byte in cache line). If total cache size is 1024 and there are 32 cache lines, where is tags+indexes are stored? (There is another 4*32 = 128 bytes.) Does it means that actual size of the cache is 1024+128 = 1152? 2) If cache line is 32

As a follow-up to this topic , in order to calculate the memory miss latency, I have wrote the following code using _mm_clflush , __rdtsc and _mm_lfence (which is based on the code from this question/answer ). As you can see in the code, I first load the array into the cache. Then I flush one element and therefore the cache line is evicted from all cache levels. I put _mm_lfence in order to preserve the order during -O3 . Next, I used time stamp counter to calculate the latency or reading array[0] . As you can see between two time stamps, there are three instructions: two lfence and one read .

I'm trying to use the WBINV instruction on linux to clear the processor's L1 cache. The following program compiles, but produces a segmentation fault when I try to run it. int main() {asm ("wbinvd"); return 1;} I'm using gcc 4.4.3 and run Linux kernel 2.6.32-33 on my x86 box. Processor info: Intel(R) Core(TM)2 Duo CPU T5270 @ 1.40GHz I built the program as follows: $ gcc $ ./a.out Segmentation Fault Can somebody tell me what I'm doing wrong? How do I get this to run? P.S: I'm running a few performance tests and want to ensure that the previous content of the processor cache does not influence