cpu-architecture

Many sources, including Microsoft , reference both the int and long type as being 4 bytes and having a range of (signed) -2,147,483,648 to 2,147,483,647. What is the point of having a long primitive type if it doesn't actually provide a larger range of values? The only things guaranteed about integer types are: sizeof(char) == 1 sizeof(char) <= sizeof(short) sizeof(short) <= sizeof(int) sizeof(int) <= sizeof(long) sizeof(long) <= sizeof(long long) sizeof(char) * CHAR_BIT >= 8 sizeof(short) * CHAR_BIT >= 16 sizeof(int) * CHAR_BIT >= 16 sizeof(long) * CHAR_BIT >= 32 sizeof(long long) * CHAR_BIT

As part of my app I'm using the NDK and was wondering if it's worth bundling x86 and mips binaries alongside the standard ARM binaries. I figured the best way would be to track what my users actually have, is there an API call to grab the processor architecture so I can pass this back to my Google analytics instance? Thanks Actually, you can get the architecture without the need for reflexion at all: String arch = System.getProperty("os.arch"); From my tests it returned armv71 and i686 . EDIT: On MIPS architecture, it either returns 'mips' or 'mips64' On 64 bit ARM/Intel, it returns 'arch64'

The default memory page size of the Linux kernel on x86 architecture was 4 KB, I wonder how was that calculated, and why ? The default page size is fixed by what the MMU (memory management unit) of the CPU supports. In 32-bit protected mode x86 supports two kinds of pages: normal ones, 4 KiB huge ones, 4 MiB Not all x86 processors support large pages. One needs to have a CPU with Page Size Extension (PSE) capabilities. This excludes pre-Pentium processors. Virtually all current-generation x86 CPUs implements it. 4 KiB is widely popuplar page granularity in other architectures too. One could

Can someone explain what's the different between Word and Byte addressable? How is it related to memory size etc.? KawaiKx A byte is a memory unit for storage A memory chip is full of such bytes . Memory units are addressable . That is the only way we can use memory . In reality, memory is only byte addressable . It means: A binary address always points to a single byte only. A word is just a group of bytes – 2 , 4 , 8 depending upon the data bus size of the CPU. To understand the memory operation fully, you must be familiar with the various registers of the CPU and the memory ports of the RAM

I just updated my iPhone 4S software to iOS 7 Beta 2 while I was in the middle of putting the final touches on a new app (Phonegap).. not a good idea! After it was done Xcode didn't detect my iPhone so I installed Xcode 5 beta. After tinkering around with it I finally got it to detect my phone. The only problem now is there is an error with the architecture used. Here are the errors being produced: ld: warning: ignoring file /Users/-----------/Library/Developer/Xcode/DerivedData/testtest-bmnbmujiosugcmgeiceofgcfmsec/Build/Products/Debug-iphoneos/libCordova.a, file was built for archive which

Starting with Pentium Pro (P6 microarchitecture), Intel redesigned it's microprocessors and used internal RISC core under the old CISC instructions. Since Pentium Pro all CISC instructions are divided into smaller parts (uops) and then executed by the RISC core. At the beginning it was clear for me that Intel decided to hide new internal architecture and force programmers to use "CISC shell". Thanks to this decision Intel could fully redesign microprocessors architecture without breaking compatibility, it's reasonable. However I don't understand one thing, why Intel still keeps an internal

In order to mitigate against kernel or cross-process memory disclosure (the Spectre attack), the Linux kernel 1 will be compiled with a new option , -mindirect-branch=thunk-extern introduced to gcc to perform indirect calls through a so-called retpoline . This appears to be a newly invented term as a Google search turns up only very recent use (generally all in 2018). What is a retpoline and how does it prevent the recent kernel information disclosure attacks? 1 It's not Linux specific, however - similar or identical construct seems to be used as part of the mitigation strategies on other OSes

What is the difference between Trap and Interrupt? If the terminology is different for different systems, then what do they mean on x86? A trap is an exception in a user process. It's caused by division by zero or invalid memory access. It's also the usual way to invoke a kernel routine (a system call ) because those run with a higher priority than user code. Handling is synchronous (so the user code is suspended and continues afterwards). In a sense they are "active" - most of the time, the code expects the trap to happen and relies on this fact. An interrupt is something generated by the

It's a common claim that a byte store into cache may result in an internal read-modify-write cycle, or otherwise hurt throughput or latency vs. storing a full register. But I've never seen any examples. No x86 CPUs are like this, and I think all high-performance CPUs can directly modify any byte in a cache-line, too. Are some microcontrollers or low-end CPUs different, if they have cache at all? ( I'm not counting word-addressable machines , or Alpha which is byte addressable but lacks byte load/store instructions. I'm talking about the narrowest store instruction the ISA natively supports.)

The Intel optimization manual talks about the number of store buffers that exist in many parts of the processor, but do not seem to talk about the size of the store buffers. Is this public information or is the size of a store buffer kept as a microarchitectural detail? The processors I am looking into are primarily Broadwell and Skylake, but information about others would be nice as well. Also, what do store buffers do, exactly? Related: what is a store buffer? The store buffer as a whole is composed of multiple entries . Each core has its own store buffer 1 to decouple execution and