cpu-architecture | 易学教程

Why did Intel change the static branch prediction mechanism over these years?

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问题 From here I know Intel implemented several static branch prediction mechanisms these years: 80486 age: Always-not-taken Pentium4 age: Backwards Taken/Forwards Not-Taken Newer CPUs like Ivy Bridge, Haswell have become increasingly intangible, see Matt G's experiment here. And Intel seems don't want to talk about it any more, because the latest material I found within Intel Document was written about ten years ago. I know static branch prediction is (far?) less important than dynamic, but in

Why are some Haswell AVX latencies advertised by Intel as 3x slower than Sandy Bridge?

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In the Intel intrinsics webapp , several operations seem to have worsened from Sandy Bridge to Haswell. For example, many insert operations like _mm256_insertf128_si256 show a cost table like the following: Performance Architecture Latency Throughput Haswell 3 - Ivy Bridge 1 - Sandy Bridge 1 - I found this difference puzzling. Is this difference because there are new instructions that replace these ones or something that compensates for it (which ones)? Does anyone know if Skylake changes this model further? Peter Cordes TL:DR : all lane-crossing shuffles / inserts / extracts have 3c latency

Is it possible to detect processor architecture in java? [duplicate]

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问题 This question already has answers here : get OS-level system information (15 answers) Closed 6 years ago . Is it possible to detect processor architecture in java? like x86 or sun SPARC, etc? If so, how would I go about doing it? 回答1: System.getProperty ("os.arch"); On my PC returns amd64 . 回答2: You can try the System.getenv() to get environment variables, use the PROCESSOR_ARCHITECTURE Key to get the CPU-architechture: System.out.println(System.getenv("PROCESSOR_ARCHITECTURE")); or in case

How can Intel and AMD be different but still compatible?

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As I have always understood it, AMD built their CPUs by reverse engineering Intel's instruction set and now pay Intel to use their instruction set, and Intel do the same for AMDs 64-bit instructions. This is how windows can be installed on both types of CPUs without needing to purchase a specific build, such as a version compiled for ARM, and so all apps, games etc work in the same way, working interchangeable on CPUs... However lately some things have been making me question some of this... Firstly, I've noticed some games have been a bit laggy on my system (AMD) and after reading it turns

Why are some Haswell AVX latencies advertised by Intel as 3x slower than Sandy Bridge?

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问题 In the Intel intrinsics webapp, several operations seem to have worsened from Sandy Bridge to Haswell. For example, many insert operations like _mm256_insertf128_si256 show a cost table like the following: Performance Architecture Latency Throughput Haswell 3 - Ivy Bridge 1 - Sandy Bridge 1 - I found this difference puzzling. Is this difference because there are new instructions that replace these ones or something that compensates for it (which ones)? Does anyone know if Skylake changes this

How can Intel and AMD be different but still compatible?

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问题 As I have always understood it, AMD built their CPUs by reverse engineering Intel's instruction set and now pay Intel to use their instruction set, and Intel do the same for AMDs 64-bit instructions. This is how windows can be installed on both types of CPUs without needing to purchase a specific build, such as a version compiled for ARM, and so all apps, games etc work in the same way, working interchangeable on CPUs... However lately some things have been making me question some of this...

Endianness Work-around Needed

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问题 Consider the following piece of code: #include "stdio.h" typedef struct CustomStruct { short Element1[10]; }CustomStruct; void F2(char* Y) { *Y=0x00; Y++; *Y=0x1F; } void F1(CustomStruct* X) { F2((char *)X); printf("s = %x\n", (*X).Element1[0]); } int main(void) { CustomStruct s; F1(&s); return 0; } At run-time, by the end of calling the function F1 , I get different results by using different compilers. (*X).Element1[0] = 0x1f00 in some compiler and (*X).Element1[0] = 0x001f with another one

entering ring 0 from user mode

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问题 Most modern operating systems run in the protected mode. Now is it possible for the user programs to enter the "ring 0" by directly setting the corresponding bits in some control registers. Or does it have to go through some syscall. I believe to access the hardware we need to go through the operating system. But if we know the address of the hardware device can we just write some assembly language code with reference to the location of the device and access it. What happens when we give the

What happens when different CPU cores write to the same RAM address without synchronization?

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Let's assume that 2 cores are trying to write different values to the same RAM address (1 byte), at the same moment of time (plus-minus eta), and without using any interlocked instructions or memory barriers. What happens in this case and what value will be written to the main RAM? The first one wins? The last one wins? Undetermined behavior? x86 (like every other mainstream SMP CPU architecture) has coherent data caches . It's impossible for two difference caches (e.g. L1D of 2 different cores) to hold conflicting data for the same cache line. The hardware imposes an order (by some

Right way to detect cpu architecture?

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I'm attempting to detect the right cpu architecture for installing either a x86 msi or x64 msi file. If I'm right, for the msi I need the os cpu architecture I'm not totally sure if my way is right because I can't test it. What do you think? private static string GetOSArchitecture() { string arch = System.Environment.GetEnvironmentVariable("PROCESSOR_ARCHITECTURE"); string archWOW = System.Environment.GetEnvironmentVariable("PROCESSOR_ARCHITEW6432"); if(archWOW != null && archWOW != "" && archWOW.Contains("64")) return "x64"; if(arch.Contains("86")) return "x86"; if (arch.Contains("64"))