bsdmake

问题 Remark This is a variation on the question “What is the purpose of linking object files separately in a Makefile?” by user4076675 taking a slightly different point of view. See also the corresponding META discussion. Let us consider the classical case of a C project. The gcc compiler is able to compile and link programs in one step. We can then easily describe the build routine with a shell script: case $1 in build) gcc -o test *.c;; clean) rm -f test;; esac # This script is intentionally

问题 OS: FreeBSD 11.0-RELEASE I have the following directory structure: /xxx/obj/ /xxx/src/deep.cpp /xxx/flat.cpp /xxx/makefile The content of makefile is as follows: flat.out: flat.o deep.out: src/deep.o I have no problem building flat: /xxx $ make flat.out c++ -O2 -pipe -c /xxx/flat.cpp -o flat.o cc -O2 -pipe flat.o -o flat.out /xxx $ ls obj flat.o flat.out But when I try to build deep it fails: /xxx $ make deep.out c++ -O2 -pipe -c /xxx/src/deep.cpp -o src/deep.o error: unable to open output

问题 I am working on a Makefile which has a¹ receipt producing some file using M4. It uses some complex shell constructions to compute macro values which have to be passed to M4. How can I organize code to avoid redundant declarations displayed in the following example? M4TOOL= m4 M4TOOL+= -D PACKAGE=$$(cd ${PROJECTBASEDIR} && ${MAKE} -V PACKAGE) M4TOOL+= -D VERSION=$$(cd ${PROJECTBASEDIR} && ${MAKE} -V VERSION) M4TOOL+= -D AUTHOR=$$(cd ${PROJECTBASEDIR} && ${MAKE} -V AUTHOR) M4TOOL+= -D RDC960=$$

问题 I am not aware of any way to define programatically targets in GNU Make. How is this possible? Sometimes one can go away with alternate methods. The ability to define programatically targets in Makefiles is however a very important to write and organise complex production rules with make . Examples of complex production rules are found in the build system of FreeBSD or in Makefile libraries such as BSD Owl The main differences between shell scripts and Makefiles are: In a Makefile, the state

问题 Apart from the fact that bmake is an BSD equivalent of GNU make, I could not clearly understand it's advantages over GNU make. Can anyone help me? I was able to find only one resource that was bit helpful. More help or pointers are appreciated. Thanks, Prabhu 回答1: BSD make and GNU make are both free replacements for the original AT&T make. The major difference is having different syntax for the advanced features. Here is how to put the output of a shell command in a variable in BSD make: #