Arithmetic shift acts as a logical shift, regardless of the signed variable
I've got a register declared as so: logic signed [15:0][2:0][15:0] registers; When I place a 2's compliment number into the array and arithmetically shift the number, it logical shifts instead: registers[0][0] = 16'b1000000000000000; registers[0][0] = registers[0][0]>>>2; Apparently, the system will logical shift instead of arithmetically shift if the number is not signed. However as you can clearly see, 'registers' is definitely signed. Does anybody know what I might be missing here? Thanks! With Verilog, once you take a part-select, the result is unsigned . Use the $signed system task on the