atomic

问题 I wanted to try and atomically reset 256 bits using something like this: #include <x86intrin.h> #include <iostream> #include <array> #include <atomic> int main(){ std::array<std::atomic<__m256i>, 10> updateArray; __m256i allZeros = _mm256_setzero_si256(); updateArray[0].fetch_and(allZeros); } but I get compiler errors about the element not having fetch_and() . Is this not possible because 256 bit type is too large to guarantee atomicity? Is there any other way I can implement this? I am using

问题 First question I found on cppreference _Atomic ( type-name ) (since C11) Use as a type specifier; this designates a new atomic type _Atomic type-name (2) (since C11) Use as a type qualifier; this designates the atomic version of type-name. In this role, it may be mixed with const, volatile, and restrict), although unlike other qualifiers, the atomic version of type-name may have a different size, alignment, and object representation. So does using _Atomic(int) instead of _Atomic int guarantee

问题 std::atomic<int> flag0(0),flag1(0),turn(0); void lock(unsigned index) { if (0 == index) { flag0.store(1, std::memory_order_relaxed); turn.exchange(1, std::memory_order_acq_rel); //turn.store(1) while (flag1.load(std::memory_order_acquire) && 1 == turn.load(std::memory_order_relaxed)) std::this_thread::yield(); } else { flag1.store(1, std::memory_order_relaxed); turn.exchange(0, std::memory_order_acq_rel); //turn.store(0) while (flag0.load(std::memory_order_acquire) && 0 == turn.load(std:

问题 The following piece of code is what one can get after they significantly simplify the hazard-pointer algorithm (introduced in this paper). Because of the gross amount of simplification, it cannot be used in place of the algorithm (and one does not need to know anything about the algorithm to answer this question ). However, I believe it still perfectly represents the memory-ordering challenge in the original algorithm. So the question is what is the best memory-ordering so that if ptr->a = 1;

问题 I am currently wading through the ARM architecture manual for the ARMv7 core. In chapter A3.5.3 about atomicity of memory accesses, it states: If a single-copy atomic load overlaps a single-copy atomic store and for any of the overlapping bytes the load returns the data written by the write inserted into the Coherence order of that byte by the single-copy atomic store then the load must return data from a point in the Coherence order no earlier than the writes inserted into the Coherence

问题 cppreference.com documents this function as "fence between a thread and a signal handler executed in the same thread". But I found no example on the Internet. I wonder whether or not the following psuedo-code correctly illustrates the function of std::atomic_signal_fence() : int n = 0; SignalObject s; void thread_1() { s.wait(); std::atomic_signal_fence(std::memory_order_acquire); assert(1 == n); // never fires ??? } void thread_2() { n = 1; s.signal(); } int main() { std::thread t1(thread_1)

问题 cppreference.com documents this function as "fence between a thread and a signal handler executed in the same thread". But I found no example on the Internet. I wonder whether or not the following psuedo-code correctly illustrates the function of std::atomic_signal_fence() : int n = 0; SignalObject s; void thread_1() { s.wait(); std::atomic_signal_fence(std::memory_order_acquire); assert(1 == n); // never fires ??? } void thread_2() { n = 1; s.signal(); } int main() { std::thread t1(thread_1)

问题 cppreference.com documents this function as "fence between a thread and a signal handler executed in the same thread". But I found no example on the Internet. I wonder whether or not the following psuedo-code correctly illustrates the function of std::atomic_signal_fence() : int n = 0; SignalObject s; void thread_1() { s.wait(); std::atomic_signal_fence(std::memory_order_acquire); assert(1 == n); // never fires ??? } void thread_2() { n = 1; s.signal(); } int main() { std::thread t1(thread_1)

问题 I am trying to understand how to safely increment a counter column, that may be incremented simultaneously by many users (It's a Web API for a mobile app). I've read the popular questions in SO for strategies dealing with the issue but I can't seem to figure what's wrong with using a simple: UPDATE Table SET Counter = Counter + 1 I've built the following code sample to try and get inconsistent values and prove myself that using only this simple update statement is not good practice: class

问题 I'm trying to implement my own read/write lock using atomic types. I can easily define exclusive locks, but I fail to create locks for shared reader threads, like SRWLock does (see SRWLock). My question is how to implement locks that can be used in exclusive mode (one reader/writer threads at a time) or in shared mode (multiple reader threads at a time). I can't use std::mutex lock because it doesn't support multiple readers. Also I don't use boost, so no shared_mutex either. 回答1: The shared