assembly

问题 I noticed that in Assembly segments are used in opcodes. Example: MOV DWORD PTR SS:[EBP-30],30 I think that "PTR SS:" is used to specify that EBP-30 comes from the stack? (SS: stack segment) Am I right or am I completely wrong? :) And, could you please tell me the difference between the example above and MOV DWORD PTR[EBP-30],30 And what about DS (data segment) used in opcodes? 回答1: MOV DWORD PTR SS:[EBP-30],30 There are two separate modifiers here, DWORD PTR and SS: . The first one tells us

问题 Im trying to move edx into al but i get this error lib/io/print.asm:50: error: invalid combination of opcode and operands this is the code mov edx, 0x41 mov al, edx thanks in advance 回答1: The problem is the second line: mov al, edx The edx register is 32-bits, but al is 8-bit, so you can't directly move one into the other. If you want to move the low 8 bits of edx into dl , do this: mov al, dl Or perhaps you want to move all of edx into eax , like this: mov eax, edx The difference is the

问题 Im trying to move edx into al but i get this error lib/io/print.asm:50: error: invalid combination of opcode and operands this is the code mov edx, 0x41 mov al, edx thanks in advance 回答1: The problem is the second line: mov al, edx The edx register is 32-bits, but al is 8-bit, so you can't directly move one into the other. If you want to move the low 8 bits of edx into dl , do this: mov al, dl Or perhaps you want to move all of edx into eax , like this: mov eax, edx The difference is the

问题 I have this memchr code that I'm trying to make non-branching: .globl memchr memchr: mov %rdx, %rcx mov %sil, %al cld repne scasb lea -1(%rdi), %rax test %rcx, %rcx cmove %rcx, %rax ret I'm unsure whether or not cmove is a branching instruction. Is it? If so, how do I rearrange my code so it doesn't branch? 回答1: No, it's not a branch, that's the whole point of cmovcc . It's an ALU select that has a data dependency on both inputs, not a control dependency . (With a memory source, it

问题 I used to benchmark Linux System Calls with rdtsc to get the counter difference before and after the system call. I interpreted the result as wall clock timer since TSC increments at constant rate and does not stop when entering halt state. The Invariant TSC concept is described as The invariant TSC will run at a constant rate in all ACPI P-, C-. and T-states. Can a constant non-invariant tsc change frequency when changing state from C0 (operating) to C1 (halted)? My current view is that it

问题 I used to benchmark Linux System Calls with rdtsc to get the counter difference before and after the system call. I interpreted the result as wall clock timer since TSC increments at constant rate and does not stop when entering halt state. The Invariant TSC concept is described as The invariant TSC will run at a constant rate in all ACPI P-, C-. and T-states. Can a constant non-invariant tsc change frequency when changing state from C0 (operating) to C1 (halted)? My current view is that it

问题 This question already has answers here : return statement vs exit() in main() (8 answers) Closed 10 days ago . Hi I wanted to know what the differences between returning and exiting from the main function are. What happens behind the scenes when each of them are invoked, and how is the control returned in each case. I would really appreaciate it if someone could dive deep into this subject. 回答1: There is no difference. Behind the scenes, what happens (at least on some popular operating

问题 I know that call and ret will modify the value of esp and that push and pop have a number of variants, but are there other instructions that will affect the stack pointer ? 回答1: The following instructions modify the stack pointer 1 : call enter int n/into/int 3 iret/iretd leave pop push ret sysenter sysexit pusha/pushad popa/popad pushf/pushfd/pushfq popf/popfd/popfq vmlaunch/vmresume eexit I leave to you the burden of telling primary and side effects apart. Keep in mind that any instruction

问题 I have a question about instruction latency on https://uops.info/. For some instructions like PCMPEQB(XMM, M128) the latency in the table entry for Skylake is listed as [1;≤8] I know a little about latency, but what i know is that it's just a single number !!! for example, 1 or 2 or 3 or ... but what is this [1;≤8] !!!??? It means latency depends on memory and it's between 1 and 8 ? If it's true, when is it 1 .. when is it 3, etc? For example, what is the latency for this : pcmpeqb xmm0,

问题 I have a question about instruction latency on https://uops.info/. For some instructions like PCMPEQB(XMM, M128) the latency in the table entry for Skylake is listed as [1;≤8] I know a little about latency, but what i know is that it's just a single number !!! for example, 1 or 2 or 3 or ... but what is this [1;≤8] !!!??? It means latency depends on memory and it's between 1 and 8 ? If it's true, when is it 1 .. when is it 3, etc? For example, what is the latency for this : pcmpeqb xmm0,