Verilog generate/genvar in an always block
可以将文章内容翻译成中文,广告屏蔽插件可能会导致该功能失效(如失效,请关闭广告屏蔽插件后再试): 问题: I'm trying to get a module to pass the syntax check in ISE 12.4, and it gives me an error I don't understand. First a code snippet: parameter ROWBITS = 4; reg [ROWBITS-1:0] temp; genvar c; generate always @(posedge sysclk) begin for (c = 0; c When I try a syntax check, I get the following error message: ERROR:HDLCompiler:731 - "test.v" Line 46: Procedural assignment to a non-register is not permitted. I really don't understand why it's complaining. "c" isn't a wire, it's a genvar. This should be the equivalent of the completely legal syntax: