Problem Description:
I design in SystemVerilog and write the testbenches in the same language. I want to be able to compile my design and test different functions during simulation in the way you would using an interpreter with e. Ideally, I would have a terminal pop-up upon simulation when the simulator hit some line.
Potential Ideas:
I've looked at the DPI-C and it seems like I would have to "export" all tasks in my project in order to run them from the interpreter. However, I'm not sure how to do this automatically or if there's a better way. Furthermore, I have no idea how I would get C to open up a second shell for me to type the SystemVerilog tasks in (that I would want to run).
This is a problem echoes by my colleagues and it would make life a lot less painful to not have to wait 10 minutes between compiling just a testbench.
Best bet is likely using DPI with some kind of scripting language for your tests. For example I have seen this work well: Python -> Boost.Python -> C++ -> DPI -> Verilog/SystemVerilog
It does limit what you can do in your test (approach it as a TLM interface between the two language, ie only pass transactions back and forth between them), but actually that usually forces you to use good abstraction practices anyway. Read up on "yield" in Python to understand how you pass control back and forth between the python and the simulator.
Hi i provide my two cents with another example.
EXAMPLE SV-CODE
C-CODE
PYTHON SCRIPT - TEST.py, very important to remove TABS!!!!!!
Lastly, you have to compile the files using your vendor flow. For example, Questa 1) You compile the C code using ccflags and introducing the defines you want to add. In our case our C code need the define PYTHON_PATH
vlog $DUT_VLOG_ARGS ${TB_DIR}/your_C_code.c -ccflags "-I/usr/include/python2.6/ -D 'PYTHON_PATH=\"$PYTHON_DIR\"'"
2) In Questa if you have python you have to call vsim including -ldflags '-lpython2.6' Something like:
vsim -ldflags '-lpython2.6' -voptargs="+acc" -solvefaildebug -assertdebug -onfinish stop +UVM_TESTNAME=${TESTCASE_STRING} yourtop_tb_top \
Synopsys VCS 1) You compile the C code using ccflags and introducing the defines you want to add. In our case our C code need the define PYTHON_PATH
#GCC in two steps for shared object gcc -g -D 'PYTHON_PATH="'$PYTHON_DIR'"' -fPIC -Wall -I${VCS_HOME}/include -I/usr/include/python2.6/ -lpython2.6 -c ${PROJECTDIR}/verification/PVE/keycontrol/tb/keycontrol_C_code_wrapper.c gcc -fPIC -shared -o keycontrol_C_code_wrapper.so keycontrol_C_code_wrapper.o
2) You do the VCS elaboration linking the python lybrary with -LDFLAGS '-lpython2.6'
vcs -timescale=1ps/1ps -ntb_opts uvm -lca -kdb -full64 keycontrol_tb_top -debug_access+all+reverse -LDFLAGS '-lpython2.6'
3) You run the created simulation file. You call simv including -sv_lib keycontrol_C_code_wrapper to import the C shared object.
#RUN C CODE ./simv -gui -ucli +DVE +UVM_NO_RELNOTES -l simv.log +UVM_TESTNAME=keycontrol_basic_test -do ../../verification/PVE/keycontrol/tools/keycontrol_ucli_init.synopsys -sv_lib keycontrol_C_code_wrapper
Another tools would have another flow.
Embedding python is a solution that is [b]more efficient[/b] than FILE IO in your python script.
If your python script reads inputs and outputs from files, then the easiest way to call python from Systemverilog is just by doing a system call.
$system("python yourscript.py filenamein filenameout ")
You have of course to write in systemverilog your input file and read in systemverilog the output file for comparison.
How about going to the simulator's interactive command line terminal. This is not a typical shell terminal such as from unix. It is an vendor specif interactive mode tied into the simulator. In most cases it is triggered with Verilog's $stop. It is vendor specific so you will need to refer to your manual for all the features, some do allow calling tasks and functions defined in Verilog/SystemVerilog.
It also sounds like you do not need to run all your conditions in one simulation. A compile once and run many strategy should work in your situation. The SystemVerilog system-functions $test$plusargs and $value$plusargs can detect the arguments used to start your simulation. See IEEE Std 1800-2012 § 21.6 Command line input
// ... int testid; // ... initial begin // ... if(!$value$pluseargs("TESTID=%d",testid)) begin // code if +TESTID= is not an argument end case(testid) 0 : run_task_test0(/*...*/); 1 : run_task_test1(/*...*/); 2 : run_task_test2(/*...*/); 3 : run_task_test3(/*...*/); // ... endcase // ... end
Then compile once and start the simulation as many times as needed.
% [compile-cmd] % [sim-cmd] +TESTID=0 % [sim-cmd] +TESTID=3 % [sim-cmd] +TESTID=1 % [sim-cmd] +TESTID=2
