vhdl quartus : left bound of range must be a constant

问题

Is there any way to use a variable(signal) inside the std_logic_vector instead of using a constant, e.g :

dout((8*index + 7) downto 8*index) <= "00000001";

in this example the signal is index
thanks in advance

回答1:

Assuming the signal or variable index is of type integer, that should work fine. If index is a signal or variable of type std_logic_vector, you'll need to convert it to an integer.

See the following simple example (which just now compiled happily in my simulator):

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
entity thingy is
    port(clk : in std_logic;
           I : in std_logic_vector(3 downto 0);
           O : out std_logic_vector(15 downto 0);
           P : in std_logic_vector(1 downto 0));
end entity thingy;

architecture behav of thingy is
begin
    process (clk)
    begin
      if (clk = '1' and clk'event) then
        O(to_integer(unsigned(P))*4 + 3 downto to_integer(unsigned(P))*4) <= I;
      end if;
    end process;
end architecture behav; --thingy

Note that this example relies upon using numeric_std rather than the synopsis packages.

Brian Drummond makes a good point that it is possible that it won't synthesize, but if it doesn't then you should probably file a bug report.

来源：https://stackoverflow.com/questions/24192103/vhdl-quartus-left-bound-of-range-must-be-a-constant