vpi

SystemVerilog looping through hierarchy

隐身守侯 提交于 2020-01-05 03:57:08
问题 I have registers instantiated in a Register block Regblock as such: DUT.Regblock.Register1 DUT.Regblock.RegisterA DUT.Regblock.RegisterABC ... All these registers have the same inner structure. I would like to simulate the effects of bit flips in these registers. //Here an attempt to do bit flips bitFlipLocation = $random; force DUT.RegBlock.Register1.reg[bitFlipLocation] = ~DUT.RegBlock.Register1.reg[bitFlipLocation]; release DUT.ABCStar1.RegBlock.Register1.reg[bitFlipLocation]; Is there a

How to get dimensions of a verilog vector port using PLI routines?

与世无争的帅哥 提交于 2019-12-24 18:16:12
问题 How can I fetch the dimensions of a vector port using the vpi PLI routines? For example, for the vector port declaration "output [2:1] out;", how can I get the left dimension as 2 and right dimension as 1? I tried using vpiRange property but it seems that vpiRange property is not supported for Ports. Thanks! Putting the code here for clarity. vpiHandle lowconn = vpi_handle(vpiLowConn, portH); int dim = 0; int ldim[10]; int rdim[10]; vpiHandle range_itr = vpi_iterate(vpiRange, lowconn );