system-verilog

问题 I\'ve recently saw this operator in a verilog/systemverilog code. logic [15:0] down_vect; logic [0:15] up_vect; down_vect[lsb_base_expr +: width_expr] up_vect [msb_base_expr +: width_expr] down_vect[msb_base_expr -: width_expr] up_vect [lsb_base_expr -: width_expr] I\'ve rarely seen this so, I\'d like to ask What is this, When and How do you use it? 回答1: That particular syntax is called an indexed part select . It's very useful when you need to select a fixed number of bits from a variable

问题 I am a little confused about how blocking and non blocking assignments are interpreted when it comes to drawing a hardware diagram. Do we have to infer that a non blocking assignment gives us a register? Then according to this statement c <= a+b , c would be a register right, but not a and b? module add (input logic clock, output logic[7:0] f); logic[7:0] a, b, c; always_ff @(posedge clock) begin a = b + c; b = c + a; c <= a + b; end assign f = c; endmodule 回答1: It's definitely a bit tricky