What is `+:` and `-:`?

问题

I\'ve recently saw this operator in a verilog/systemverilog code.

logic [15:0] down_vect;
logic [0:15] up_vect;

down_vect[lsb_base_expr +: width_expr]
up_vect  [msb_base_expr +: width_expr]
down_vect[msb_base_expr -: width_expr]
up_vect  [lsb_base_expr -: width_expr]

I\'ve rarely seen this so, I\'d like to ask What is this, When and How do you use it?

回答1:

That particular syntax is called an indexed part select. It's very useful when you need to select a fixed number of bits from a variable offset within a multi-bit register.

Here's an example of the syntax:

reg [31:0] dword;
reg [7:0] byte0;
reg [7:0] byte1;
reg [7:0] byte2;
reg [7:0] byte3;

assign byte0 = dword[0 +: 8];    // Same as dword[7:0]
assign byte1 = dword[8 +: 8];    // Same as dword[15:8]
assign byte2 = dword[16 +: 8];   // Same as dword[23:16]
assign byte3 = dword[24 +: 8];   // Same as dword[31:24]

The biggest advantage with this syntax is that you can use a variable for the index. Normal part selects in Verilog require constants. So attempting the above with something like dword[i+7:i] is not allowed.

So if you want to select a particular byte using a variable select, you can use the indexed part select.

Example using variable:

reg [31:0] dword;
reg [7:0] byte; 
reg [1:0] i;

// This is illegal due to the variable i, even though the width is always 8 bits
assign byte = dword[(i*8)+7 : i*8];  // ** Not allowed!

// Use the indexed part select 
assign byte = dword[i*8 +: 8];

回答2:

The purpose of this operator is when you need to access a slice of a bus, both MSB position and LSB positions are variables, but the width of the slice is a constant value, as in the example below:

bit[7:0] bus_in = 8'hAA;
int lsb = 3;
int msb = lsb+3;  // Setting msb=6, for out bus of 4 bits

bit[3:0] bus_out_bad = bus_in[msb:lsb]; // ILLEGAL - both boundaries are variables
bit[3:0] bus_out_ok  = bus_in[lsb+:3]; // Good - only one variable

来源：https://stackoverflow.com/questions/17778418/what-is-and