What is the difference between Verilog ! and ~?
问题 So it ended up that the bug that had kept me on for days, was a section of code that should have evaluated to False evaluating to True. My initial code went something like: if(~x && ~y) begin //do stuff end i.e. If x is NOT ONE and y is NOT ONE then do stuff. Stepping through the debugger, I realized even though x was 1 the expression in the if-statement still resulted into TRUE and the subsequent code was executed. However, when I changed the statement to: if(x == 0 && y == 0) begin //do