modelsim | 易学教程

VHDL - DE0 - QUARTUS II PLL not showing output in modsim

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问题 Hi I am trying to use a phased lock loop for clock generation for a VGA controller. I had no luck and decided to make my own clock which then worked fine. I got the VGA controller working. Going back to PLL's though I still can't get a PLL selected to give me an output. I have made a little test model to simulate it. LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY PLL4 IS PORT ( clk : IN std_logic; a : IN std_logic; rst : IN std_logic:='0'; x : OUT std_logic ); END ENTITY PLL4; ARCHITECTURE

Altera Quartus falsly says Modelsim isn't installed

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问题 Installed Quartus 13.0 with Modelsim in Fedora 22 64-bit. Running Quartus in 32-bit because I get lots and lots of problems otherwise. However, I can start Quartus, create a project, synthesize it, fire up the simulation window and configure the in signals. Then, when clicking the button for launching Modelsim, it starts doing it's job, but ends up with ModelSim-Altera was not found. Please install ModelSim-Altera which is included with the Quartus II installer, or use the Quartus II

VHDL - Why does using the length attribute directly on a function produce a warning?

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问题 I have a VHDL function that returns a std_logic_vector representation of a record and I want the length of that std_logic_vector. I am able to use the length attribute directly on the function. Why does this produce a warning in ModelSim? Am I inviting subtle problems? Googling the warning text did not turn up anything I understood to be helpful. my_function_returns_slv(my_record)'length; ** Warning: ../src/my.vhd(line#): (vcom-1515) Prefix of predefined attribute "length" is function call

How can I make Modelsim warn me about 'X' signal?

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问题 I am working on large design using Modelsim. I've read about the way modelsim simulation works. I am wondering, is there a way that when modelsim evaluates a signal in the simulation phase and it found it to be a red signal, i.e. 'X', to warn me about it? Knowing that is impossible to list all the signals of the design and look at them one by one. Also it's very hard to put assertion command for all signals. 回答1: You can use the when command to carry out a desired action when a condition is

Quartus II 15.0 使用 ModelSim SE-64 2019.2 软件进行仿真

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Quartus II 15.0 使用 ModelSim SE-64 2019.2 软件进行仿真 ModelSim 仿真 Verilog HDL 时需要编写一个 TestBench 仿真文件，通过仿真文件提供激励信号。可以简单的理解成信号发生器，给我们的代码提供模拟时钟信号。因此编写 TestBench 仿真文件是仿真过程中的一个重要步骤。 Quartus II 15.0自身是不提供仿真功能的，但是可以用 Quartus II 15.0 创建 TestBench 仿真文件模板，而我们稍微修改一下这个生成的模板文件就能进行仿真了，非常方便。准备一个可以编译正常的工程（如果编译有问题可以参考上一篇博客）使用 Quartus II 创建 TestBench 模板文件，如下如图：创建的文件后缀名是 .vt ，自动保存在工程目录\simulation\modelsim 中，我这里是 top.vt 文件打开 top.vt 文件，文件内容如下：修改 top.vt 文件 TestBench 仿真文件修改完成，接下来使用仿真文件：下面一路 OK 结束就可以了，然后再全编译一次，切记一定是全编译，编译完成后启动仿真软件，如下图：启动仿真运行后 Quartus II 会自动打开 ModelSim 软件，ModelSim 软件打开后会自动编译仿真文件，然后加载仿真文件中的接口

Why can't I call a function in a constant declaration, that is defined in the same package in ModelSim?

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I have a VHDL package that defines a function (forward declaration) and a constant. The constant's value is calculated by that function, whose body is located in the package body. As of now ModelSim/QuestaSim is the only tool that does not like this code. It needs 2 packages so the body was parsed before the constant declaration. package test is function mytest(param : boolean ) return boolean; constant value : boolean := mytest(TRUE); end package; package body test is function mytest(param : boolean ) return boolean is begin return not param; end function; end package body; Is this not

Is there a way to toggle leaf names in ModelSim through the TCL API?

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问题 I am looking for a way to toggle leaf names of the nets in ModelSim view, in GUI mode. In other words, an equivalent of pressing "Toggle leaf names <-> full names" button: I am aware of the way of adding short names. For example, I've been using code like this: add wave -group "stimulus" -label "valid" ${sim_module}/aso_src0_valid add wave -group "stimulus" -label "ready" ${sim_module}/aso_src0_ready add wave -group "stimulus" -label "data" -radix ascii ${sim_module}/aso_src0_data add wave

ISE post-place&route仿真准备

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ISE post-place&route仿真准备使用目的：post-place&route仿真是综合后考虑门延时而进行的仿真。因为考虑到各个门的延时，所以可以发现行为仿真（behavior simulation）发现不了的问题。前期准备：因为我使用的modelsim进行的仿真，所以以下解释为基于modelsim。 1.编译库文件。因为modelsim需要调用xilinx内部元件库的各个门延时数据，所以需要将xilinx内部的simprim_ver库进行编译，并把这个库的地址放到modelsim的库调用文件modelsim.ini中去。具体做法参见xilinx给出的library编译过程，我们的目标是编译simprim_ver库。以下两图解释了编译方法。详见xilinx官方文档https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/pp_p_process_compile_hdl_simulation_libraries.htm， https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_simulation_libraries.htm 2.modelsim引用库文件。记住刚刚simprim_ver库的编译地址

How can I make Modelsim warn me about 'X' signal?

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I am working on large design using Modelsim. I've read about the way modelsim simulation works. I am wondering, is there a way that when modelsim evaluates a signal in the simulation phase and it found it to be a red signal, i.e. 'X', to warn me about it? Knowing that is impossible to list all the signals of the design and look at them one by one. Also it's very hard to put assertion command for all signals. You can use the when command to carry out a desired action when a condition is met. The find command can extract signals from the design hierarchy. Look at the Modelsim command reference

Is there a way to toggle leaf names in ModelSim through the TCL API?

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I am looking for a way to toggle leaf names of the nets in ModelSim view, in GUI mode. In other words, an equivalent of pressing "Toggle leaf names <-> full names" button: I am aware of the way of adding short names. For example, I've been using code like this: add wave -group "stimulus" -label "valid" ${sim_module}/aso_src0_valid add wave -group "stimulus" -label "ready" ${sim_module}/aso_src0_ready add wave -group "stimulus" -label "data" -radix ascii ${sim_module}/aso_src0_data add wave -group "stimulus" -label "begin" ${sim_module}/aso_src0_startofpacket add wave -group "stimulus" -label

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