VHDL: Finding out/reporting bit width/length of integer (vs. std_logic_vector)?
问题 Say I need a signal to represent numbers from 0 to 5; obviously this needs 3 bits of std_logic to be represented ( i.e if MAXVAL=5, then bitwidth= { wcalc "floor(logtwo($MAXVAL))+1" } ). I'm aware I could do: SIGNAL myLogicVector : STD_LOGIC_VECTOR(2 downto 0) := 5; with which I'd explicitly specify an array of three std_logic 'bits', and set initial value; then I could use REPORT to print out the length (in this case, 3): report("Bit width of myLogicVector is "& integer'image(myLogicVector