When should I use reg instead of wire? [duplicate]
问题 This question already has answers here : Using wire or reg with input or output in Verilog (5 answers) Closed 3 years ago . I'm confused about reg and wire when I was doing my homework. I could not understand differences between reg and wire exactly. Can you explain shortly? Also, I wonder that what will happen when I use output q instead of output reg q ? 回答1: In simulation , a Verilog wire behaves like a piece of metal, a track, a wire, whilst a Verilog reg is a variable, it is storage*.