intrinsics

I am trying to figure out a reasonably fast bilinear filtering function just for one filtered sample at a time now as an exercise in getting used to using intrinsics - up to SSE41 is fine. So far I have the following: inline __m128i DivideBy255_8xUint16(const __m128i value) { // Blinn 16bit divide by 255 trick but across 8 packed 16bit values const __m128i plus128 = _mm_add_epi16(value, _mm_set1_epi16(128)); const __m128i plus128ThenDivideBy256 = _mm_srli_epi16(plus128, 8); // TODO: Should this be an arithmetic or logical shift or does it matter? const __m128i partial = _mm_add_epi16(plus128,

Most C++ compilers support SIMD(SSE/AVX) instructions with intrisics like _mm_cmpeq_epi32 My problem with this is that this function is not marked as constexpr , although "semantically" there is no reason for this function to not be constexpr since it is a pure function. Is there any way I could write my own version of (for example) _mm_cmpeq_epi32 that is constexpr ? Obviously I would like that the function at runtime uses the proper asm, I know I can reimplement any SIMD function with slow function that is constexpr . If you wonder why I care about constexpr of SIMD functions. Non

When reading through CUDA 5.0 Programming Guide I stumbled on a feature called "Funnel shift" which is present in 3.5 compute-capable device, but not 3.0. It contains an annotation "see reference manual", but when I search for the "funnel shift" term in the manual, I don't find anything. I tried googling for it, but only found a mention on http://www.cudahandbook.com , in the chapter 8: 8.2.3 Funnel Shift (SM 3.5) GK110 added a 64-bit “funnel shift” instruction that may be accessed with the following intrinsics: __funnelshift_lc(): returns most significant 32 bits of a left funnel shift. _

I can't find them in the Intel Intrinsic Guide v2.7. Do you know if AVX or AVX2 instruction sets support them? There are no scatter or gather instructions in the original AVX instruction set. AVX2 adds gather, but not scatter instructions. AVX512F includes both scatter and gather instructions. AVX512PF additionally provides prefetch variants of gather and scatter instructions. AVX512CD provides instructions to detect conflicts in scatter addresses. Intel MIC (aka Xeon Phi, Knights Corner) does include gather and scatter instructions, but it is a separate coprocessor, and it can not run normal

I'm processing an image by four pixels at the time, this on a armv7 for an Android application. I want to divide a float32x4_t vector by another vector but the numbers in it are varying from circa 0.7 to 3.85 , and it seems to me that the only way to divide is using right shift but that is for a number which is 2^n . Also, I'm new in this, so any constructive help or comment is welcomed. Example: How can I perform these operations with NEON intrinsics? float32x4_t a = {25.3,34.1,11.0,25.1}; float32x4_t b = {1.2,3.5,2.5,2.0}; // somthing like this float32x4 resultado = a/b; // {21.08,9.74,4.4

how to use the Multiply-Accumulate intrinsics provided by GCC? float32x4_t vmlaq_f32 (float32x4_t , float32x4_t , float32x4_t); Can anyone explain what three parameters I have to pass to this function. I mean the Source and destination registers and what the function returns? Help!!! Simply said the vmla instruction does the following: struct { float val[4]; } float32x4_t float32x4_t vmla (float32x4_t a, float32x4_t b, float32x4_t c) { float32x4 result; for (int i=0; i<4; i++) { result.val[i] = b.val[i]*c.val[i]+a.val[i]; } return result; } And all this compiles into a singe assembler

The intrinsics guide says only this much about void _mm_prefetch (char const* p, int i) : Fetch the line of data from memory that contains address p to a location in the cache heirarchy specified by the locality hint i. Could you list the possible values for int i parameter and explain their meanings? I've found _MM_HINT_T0 , _MM_HINT_T1 , _MM_HINT_T2 , _MM_HINT_NTA and _MM_HINT_ENTA , but I don't know whether this is an exhaustive list and what they mean. If processor-specific, I would like to know what they do on Ryzen and latest Intel Core processors. Sometimes intrinsics are better