instruction-set

32 bit PPC rlwinm instruction

由 我是研究僧i 提交于 2019-12-11 02:36:20
问题 I'm having a bit of trouble understanding the rlwinm PPC Assembly instruction (Rotate Left Word Immediate Then AND with Mask). I am trying to reverse this part of a function rlwinm r3, r3, 0, 28, 28 I already know what r3 is. r3 in this case is a 4 byte integer but I am not sure exactly what this instruction rlwinm is doing to it. By the way, this is on a 32 bit machine. 回答1: Your understanding is not quite right. As per the IBM link on this instruction, the form you're seeing is: rlwinm

How to use Intel's RDRAND using inline assembly with .Net

由 霸气de小男生 提交于 2019-12-10 23:14:53
问题 I'm using an Intel Ivy Bridge CPU and want to use the RDRAND opcode (https://software.intel.com/en-us/articles/intel-digital-random-number-generator-drng-software-implementation-guide) in C#. How can I call this CPU instruction via C#? I've seen an example of executing assembly code from c# here: x86/x64 CPUID in C# But I'm not sure how to use it for RDRAND. The code doesn't need to check whether the CPU executing the code supports the instruction or not. I've seen this C++ example of

If a computer can be Turing complete with one instruction what is the purpose of having many instructions?

由 夙愿已清 提交于 2019-12-10 19:46:19
问题 I understand the concept of a computer being Turing complete ( having a MOV or command or a SUBNEG command and being able to therefore "synthesize" other instructions such as ). If that is true what is the purpose of having 100s of instructions like x86 has for example? Is to increase efficiency? 回答1: Yes. Equally, any logical circuit can be made using just NANDs. But that doesn't make other components redundant. Crafting a CPU from NAND gates would be monumentally inefficient, even if that

Most recent processor without support of SSSE3 instructions? [closed]

由 半世苍凉 提交于 2019-12-10 17:18:53
问题 Closed. This question is off-topic. It is not currently accepting answers. Want to improve this question? Update the question so it's on-topic for Stack Overflow. Closed last year . Are there any still-relevant CPUs (Intel/AMD/Atom) which don't support SSSE3 instructions? What's the most recent CPU without SSSE3? 回答1: The most recent CPUs without SSSE3 are based on the AMD K10 microarchitecture: AMD Phenom II , the last-generation K10 socketed desktop CPUs before Bulldozer-family. They were

does gcc's __builtin_cpu_supports check for OS support?

由 一曲冷凌霜 提交于 2019-12-10 13:18:52
问题 GCC compiler provides a set of builtins to test some processor features, like availability of certain instruction sets. But, according to this thread we also may know certain cpu features may be not enabled by OS. So the question is: do __builtin_cpu_supports intrinsics also check if OS has enabled certain processor feature? 回答1: No. I disabled AVX on my Skylake system by adding noxsave to the Linux kernel boot options. When I do cat /proc/cpuinfo AVX (and AVX2) no longer appear and when I

About arm pc value in thumb 16/32bits mixed instructions stream

由 偶尔善良 提交于 2019-12-08 23:15:30
I read a couple of articles including question here in SO Why does the ARM PC register point to the instruction after the next one to be executed? , that pc register value is actually current executing instruction address plus 2 instructions ahead, so in ARM state it's +8 byte (2*32bits). My question is that, for thumb state, there could be 16bits or 32bits instructions, does it mean that the fetching pc address could be an offset of +4 bytes OR +8 bytes for 16/32bits instructions respectively? For example: 279ae6: f8df 9338 ldr.w r9, [pc, #824] --> pc value= 279aea or 279aee 279aea: f44f 7380

What's the point of the VPERMILPS instruction (_mm_permute_ps)?

由 一世执手 提交于 2019-12-08 15:31:35
问题 The AVX instruction set introduced VPERMILPS which seems to be a simplified version of SHUFPS (for the case where both input registers are the same). For example, the following instruction: c5 f0 c6 c1 00 vshufps xmm0,xmm1,xmm1,0x0 can be replaced with: c4 e3 79 04 c1 00 vpermilps xmm0,xmm1,0x0 As you can see, the VPERMILPS version takes one byte extra and does the same thing. According to the instruction tables, both of the instructions take 1 CPU cycle and have the same throughput. What's

Pushing imm32 ends up in pushing imm64? [duplicate]

由 扶醉桌前 提交于 2019-12-08 08:48:05
问题 This question already has answers here : How many bytes does the push instruction push onto the stack when I don't specify the operand size? (2 answers) push on 64bit intel osx (4 answers) Closed last year . From the intel instruction reference: 68 id PUSH imm32 It means pushing dword-sized immediates is valid in 64-bit program. So I wrote the following program: section .text global _start _start: call _foo mov rax, 60 syscall _foo: push word 0xFFFF ;ok pop ax ;ok push dword 0xFFFFFFFF ;

About arm pc value in thumb 16/32bits mixed instructions stream

由 假如想象 提交于 2019-12-08 05:00:31
问题 I read a couple of articles including question here in SO Why does the ARM PC register point to the instruction after the next one to be executed?, that pc register value is actually current executing instruction address plus 2 instructions ahead, so in ARM state it's +8 byte (2*32bits). My question is that, for thumb state, there could be 16bits or 32bits instructions, does it mean that the fetching pc address could be an offset of +4 bytes OR +8 bytes for 16/32bits instructions respectively

How many byes is each instruction compiled to in x86 assembly?

由 百般思念 提交于 2019-12-07 01:32:30
问题 0x004012d0 <main+0>: push %ebp 0x004012d1 <main+1>: mov %esp,%ebp 0x004012d3 <main+3>: sub $0x28,%esp If the address is not available , can we calculate it ourselves? I mean we only have this: push %ebp mov %esp,%ebp sub $0x28,%esp 回答1: amount of bytes is difference of addresses between adjacent instructions: 0x004012d0 <main+0>: push %ebp ;1 byte 0x004012d1 <main+1>: mov %esp,%ebp ;2 bytes 0x004012d3 <main+3>: sub $0x28,%esp if you have only text then go here: http://www.swansontec.com
订阅 instruction-set