instruction-set

问题 I am reading a book "Computer Organization and Design RISC-V Edition" , and I came across the encoding for S-B and U-J instruction types. Those types I have mentioned above has strange encoded immediate field. S-B types separate the immediate field into 2 parts. This makes sense since all instructions encoding has to be similar. But I cannot understand why the immediate field is encoded in this way below. imm[12, 10:5], imm[4:1, 11] instead of imm[11:5], imm[4:0] U-J types also have this

问题 I have read this answer, but I need to know what is the longest instruction length on Intel 386(which is 32-bit not 64 bit) without using any instruction prefixes. Based on the manual, it is probably 12: Opcode: 2 bytes MOD/Rm: 1 byte SIB: 1 byte Displacement: 4 bytes Immediate: 4 bytes Total: 12 Is this the correct answer? 回答1: On 80386 that would be 11 bytes: Opcode: 1 byte MOD/RM: 1 byte SIB: 1 byte Displacement: 4 bytes Immediate: 4 bytes The 2-byte opcodes are using the 0Fh instruction

问题 I am reading about x86-64 (and assembly in general) through the book "computer systems a programmer's perspective"(3rd edition). The author, in compliance with other sources from the web, states that idivq takes one operand only - just as this one claims. But then, the author, some chapters later, gives an example with the instruction idivq $9, %rcx . Two operands? I first thought this was a mistake but it happens a lot in the book from there. Also, the dividend should be given from the

问题 I'm reading the book The RISC-V Reader: An Open Architecture Atlas . The authors, to explain the isolation of an ISA ( Instruction Set Architecture ) from a particular implementation (i.e., microarchitecture) wrote: The temptation for an architect is to include instructions in an ISA that helps performance or cost of one implementation at a particular time, but burden different or future implementations. As far as I understand, it states that when designing an ISA, the ISA should ideally

问题 I was reading about instruction set in wiki and I came across this paragraph: Some virtual machines that support bytecode as their ISA such as Smalltalk, the Java virtual machine, and Microsoft's Common Language Runtime, implement this by translatin the bytecode for commonly used code paths into native machine code. In addition, these virtual machines execute less frequently used code paths by interpretation (see: Just-in-time compilation). Transmeta implemented the x86 instruction set atop

问题 For sake of example, imagine i was building a virtual machine. I have a byte array and a while loop, how do i know how many bytes to read from the byte array for the next instruction to interpret a intel 8086 like instruction? EDIT: (commented) the cpu reads the opcode at the instruction pointer, with 8086 and CISC you have one byte and two byte instructions. How do i know if the next instruction is F or FF? EDIT: Found a ansew myself in this peice of text on http://www.swansontec.com/sintel

问题 I have read different things about how a memory barrier works. For example, the user Johan 's answer in this question says that a memory barrier is an instruction that the CPU executes. While the user Peter Cordes 's comment in this question says the following about how the CPU reorders instructions: It reads faster than it can execute, so it can see a window of upcoming instructions. For details, see some of the links in the x86 tag wiki, like Agner Fog's microarch pdf, and also David Kanter

问题 In the MIPS ISA, there's a zero register ( $r0 ) which always gives a value of zero. This allows the processor to: Any instruction which produces result that is to be discarded can direct its target to this register To be a source of 0 It is said in this source that this improved the speed of the CPU. How does it improve performance? And what are the reasons why not all ISA adopt this zero register? $r0 is not general purpose. It is hardwired to 0. No matter what you do to this register, it

问题 I am reading the ia-32 instruction format and found that ModR/M is one byte if required, but how to determine if it is required, someone says it is determined by Opcode , but how? I want to know the details, and is there some useful and authoritative documents which explain the details? 回答1: Intel's vol.2 manual has details on the encoding of operands for each form of each instruction. e.g. taking just the 8-bit operand size versions of the well-known add instruction, which has 2 reg,rm forms

问题 I learned about one address, two address, and three address instruction, but now I'd like to know, what kind of address instruction does x86 use? 回答1: x86 is a register machine, where at most 1 operand for any instruction can be an explicit memory address instead of a register, using an addressing mode like [rdi + rax*4] . (There are instruction which can have 2 memory operands with one or both being implicit, though: What x86 instructions take two (or more) memory operands?) Typical x86