How to write to two output ports from inside architecture in VHDL?
问题 I encountered a problem when trying to connect a component to two output ports of parent hierarchy in VHDL. Since the physical connection can be done only via "port map" statement, there is no way to connect local signal to more than one output port. Here is an example: The description of the above circuit should be smth. like this: entity HIER is port ( IN1 : in bit; OUT1, OUT2 : out bit); end hier; architecture HIER_IMPL of HIER is component BUF is port (a : in bit; o : out bit); end