How to write to two output ports from inside architecture in VHDL?

问题

I encountered a problem when trying to connect a component to two output ports of parent hierarchy in VHDL. Since the physical connection can be done only via "port map" statement, there is no way to connect local signal to more than one output port. Here is an example:

The description of the above circuit should be smth. like this:

entity HIER is
port (
    IN1 : in bit;
    OUT1, OUT2 : out bit);
end hier;

architecture HIER_IMPL of HIER is 
   component BUF is 
      port (a : in bit; o : out bit);
   end component;
begin
   BUF1 : BUF port map (a => IN1, o => OUT1, o => OUT2);
end HIER_IMPL;

However, double assignment of output port "o" to both OUT1 and OUT2 won't work as it is prohibited in VHDL.

回答1:

Is there a reason why you cannot create an internal signal and use that signal to drive the two output ports like this?

entity HIER is
port (
    IN1 : in bit;
    OUT1, OUT2 : out bit);
end hier;

architecture HIER_IMPL of HIER is 
   signal temp : bit;
   component BUF is 
      port (a : in bit; o : out bit);
   end component;
begin
   BUF1 : BUF port map (a => IN1, o => temp);
   OUT1 <= temp;
   OUT2 <= temp;

end HIER_IMPL;

If this is not possible, how about this?

entity HIER is
port (
    IN1 : in bit;
    OUT1, OUT2 : out bit);
end hier;

architecture HIER_IMPL of HIER is 
   component BUF is 
      port (a : in bit; o : out bit);
   end component;
begin
   BUF1 : BUF port map (a => IN1, o => OUT1);
   BUF2 : BUF port map (a => IN1, o => OUT2);
end HIER_IMPL;

来源：https://stackoverflow.com/questions/12144019/how-to-write-to-two-output-ports-from-inside-architecture-in-vhdl

标签

variable-assignment

instantiation

vhdl