cortex-m

How to delay an ARM Cortex M0+ for n cycles, without a timer?

a 夏天 提交于 2019-11-30 15:34:37
I want to delay an ARM Cortex M0+ for n cycles, without using a timer, with the smallest possible code size. (I think this mandates use of assembly.) A delay of 0 cycles is simple no code. A delay of 1 cycle is a single NOP. A delay of 2 cycles is two NOPs. At what point is it (code-size) efficient to start looping? How many cycles does the tightest possible loop take? What is the setup time? Post answer notes: The following C code: register unsigned char counter = 100; while (counter-- > 0) { asm(""); } when compiled with gcc and -O3 gives: mov r3, #100 .L5: sub r3, r3, #1 uxtb r3, r3 cmp r3,

ARM Cortex-M compiler differences

人走茶凉 提交于 2019-11-30 02:37:17
问题 I'm about to develop some firmwares for Cortex-M cores on STM32 processors using C for my projects, and searching on the web I've found a lot of different compilers: Keil, IAR, Linaro, Yagarto and GNU Tools for ARM Embedded Processors. I was wondering, what functional differences are there between these compilers that might influence my choice? For example as an enthusiast I don't need support or assistance from the vendor, and a limitation on the code size is OK for the moment. Also the ease

Declaring abstract class (pure virtual method) increase binary size substantially

陌路散爱 提交于 2019-11-29 20:41:43
问题 Here is the story: I am developing C++ software for ARM Cortex-M0 processor in Linux with AC6 Toolpack. Before I was using Keil (in windows) (who has their own toolchain) and I have migrated to GNU-toolchain ((GNU Tools for ARM Embedded Processors) 5.2.1) . First thing i have realized is; binary file size increased substantially. I have tested every compiler optimizations (except link time optimization, it gives an error in inline assembly, not part of question but may be related to answer).

Unaligned access causes error on ARM Cortex-M4

[亡魂溺海] 提交于 2019-11-28 07:03:32
I have an object that has an address that is not 4-byte aligned. This causes a HardFault error in the cpu when there is a STR instruction saving 2 registers. This is the generated code: 00000000 <_ZN8BaseAreaC1EPcmm>: 0: b510 push {r4, lr} 2: 4604 mov r4, r0 4: 6042 str r2, [r0, #4] 6: e9c4 3102 strd r3, r1, [r4, #8] a: 2001 movs r0, #1 c: 7420 strb r0, [r4, #16] e: b921 cbnz r1, 1a <_ZN8BaseAreaC1EPcmm+0x1a> These are the registers when at line "4: 6042..." R0 08738B82 R8 0 R1 08738BAE R9 0 R2 0 R10 082723E0 R3 2FCC R11 0 R4 08738B82 R12 0 R5 20007630 R13 2000CB38 As seen the target register

Bootloader for Cortex M3

瘦欲@ 提交于 2019-11-27 16:15:36
问题 I am using a LPC 1768 board from mbed, (with cortex M3 cpu) and I am trying to achieve something here, mainly upgrade the user application from the SD Card, I am writing two programs, first a bootloader/nano-kernel, and a user-app (helloworld will do for a start): Bootloader/nano-kernel at 0x00 address runs, it will do some checks and eventually grab the binary file on the SD card Bootloader/nano-kernel will copy this binary at address 0x9000 (that might have to change later on, but this

Unaligned access causes error on ARM Cortex-M4

牧云@^-^@ 提交于 2019-11-27 01:41:55
问题 I have an object that has an address that is not 4-byte aligned. This causes a HardFault error in the cpu when there is a STR instruction saving 2 registers. This is the generated code: 00000000 <_ZN8BaseAreaC1EPcmm>: 0: b510 push {r4, lr} 2: 4604 mov r4, r0 4: 6042 str r2, [r0, #4] 6: e9c4 3102 strd r3, r1, [r4, #8] a: 2001 movs r0, #1 c: 7420 strb r0, [r4, #16] e: b921 cbnz r1, 1a <_ZN8BaseAreaC1EPcmm+0x1a> These are the registers when at line "4: 6042..." R0 08738B82 R8 0 R1 08738BAE R9 0