cortex-m

ARM架构体系

守給你的承諾、 提交于 2019-12-04 03:47:38
架构 处理器家族 ARMv1 ARM1 ARMv2 ARM2 、 ARM3 ARMv3 ARM6, ARM7 ARMv4 StrongARM 、 ARM7TDMI 、 ARM9 TDMI ARMv5 ARM7EJ 、 ARM9E 、 ARM10E 、 XScale ARMv6 ARM11 、 ARM Cortex-M ARMv7 ARM Cortex-A 、 ARM Cortex-M 、 ARM Cortex-R ARMv8 Cortex-A50 [9] 参考: 【arm cpu架构体系】【armV8】【armv7】【A系列的CPU】 来源: https://www.cnblogs.com/embedded-linux/p/11829416.html

arm sleep mode entry and exit differences WFE, WFI

大城市里の小女人 提交于 2019-12-04 02:47:36
I am reasonably new to the ARM architectures and I am trying to wrap my head around the wake up mechanism. So first of all I am finding it difficult to find good info on this. ARM's documentation seems to be very terse on the topic. What I'd like to understand is when the Cortex (particularly the M0 as that's what I am working with) will wake up. For reference, I have also consulted the following: What is the purpose of WFI and WFE instructions and the event signals? Why does the processor enter standby when using WFE instruction but not when using WFI instruction? The docs on the WFE

How to create a QEMU ARM machine with custom peripherals and memory maps?

て烟熏妆下的殇ゞ 提交于 2019-12-03 02:44:42
问题 I am writing a code for Cortex-M3 cpu and I am performing unit testing using qemu-arm binary. For now everything works just fine. But I am wondering If I am able to test whole system using qemu-system-arm ? I mean, I want to write custom "machine" for qemu where I will define desired memory map and eventually some software imitation of desired peripherals, are there some examples of such module? I found very little amount of information about this. I have read some source code in hw directory

ARM M4 Instructions per Cycle (IPC) counters

半腔热情 提交于 2019-12-03 01:11:46
I would like to count the number of Instructions per Cycle executed on an ARM cortex-M4 (or cortex-M3) processor. What it's needed is: number of instructions (executed at runtime) of the code I want to profile and number of cycles that the code takes to execute. 1 - Number of Cycles Use the cycle counter is quite easy and straightforward. volatile unsigned int *DWT_CYCCNT ; volatile unsigned int *DWT_CONTROL ; volatile unsigned int *SCB_DEMCR ; void reset_timer(){ DWT_CYCCNT = (int *)0xE0001004; //address of the register DWT_CONTROL = (int *)0xE0001000; //address of the register SCB_DEMCR =

Cortex-M单片机下载数据到外部flash

匿名 (未验证) 提交于 2019-12-03 00:37:01
主机环境:Windows 10 64bit 开发环境:MDK 5.23 目标板:LPC54114 之前在NXP社区得到一块LPC54114的板卡,是由万利制作的,LPC54114是一款双核MCU,包含了一颗M4主核和一颗M0+从核,利用该板卡学习了一下双核MCU的开发流程,板卡中提供了一颗W25P80FLASH,之前拥有的板卡都没有挂外部FLASH,刚好之前利用LPC54608学习TouchGFX时可以把图片资源下载到外部FLASH中,因此借此机会来学习一下如何把数据下载到外部FLASH。 平时烧录代码我们都是烧录到MCU内部的FLASH中,如下图: 可以看到下载的时片上256KB的FLASH,该算法文件是由DFP包提供的,具体可以在keil5的安装目录下找到,如下: 加载到内部FLASH的算法有了,但加载到外部FLASH的算法还没得。keil5中提供了LPC54608板卡的外部FLASH算法,LPC54114的外部FLASH算法就需要我们自己实现了,而且我们的板卡不是NXP官方的板卡,更不可能提供外部FLASH的加载算法了。。。 进入到keil的FLASH目录,如下: 拷贝LPC5460x_MT25QL128文件夹到LPC54114_W25P80文件夹,并把其中有关信息全部替换成LPC54114相关信息。keil中提供了FlashOS.h头文件

How to create a QEMU ARM machine with custom peripherals and memory maps?

自古美人都是妖i 提交于 2019-12-02 16:41:49
I am writing a code for Cortex-M3 cpu and I am performing unit testing using qemu-arm binary. For now everything works just fine. But I am wondering If I am able to test whole system using qemu-system-arm ? I mean, I want to write custom "machine" for qemu where I will define desired memory map and eventually some software imitation of desired peripherals, are there some examples of such module? I found very little amount of information about this. I have read some source code in hw directory in qemu source tree but it is almost all uncommented, and I am still not sure if I understand how to

Can DMB instructions be safely omitted in ARM Cortex M4

这一生的挚爱 提交于 2019-12-01 12:38:24
I am going through the assembly generated by GCC for an ARM Cortex M4, and noticed that atomic_compare_exchange_weak gets two DMB instructions inserted around the condition (compiled with GCC 4.9 using -std=gnu11 -O2 ): // if (atomic_compare_exchange_weak(&address, &x, y)) dmb sy ldrex r0, [r3] cmp r0, r2 itt eq strexeq lr, r1, [r3] cmpeq.w lr, #0 dmb sy bne.n ... Since the programming guide to barrier instructions for ARM Cortex M4 states that: Omitting the DMB or DSB instruction in the examples in Figure 41 and Figure 42 would not cause any error because the Cortex-M processors: do not re

Can DMB instructions be safely omitted in ARM Cortex M4

感情迁移 提交于 2019-12-01 11:39:14
问题 I am going through the assembly generated by GCC for an ARM Cortex M4, and noticed that atomic_compare_exchange_weak gets two DMB instructions inserted around the condition (compiled with GCC 4.9 using -std=gnu11 -O2 ): // if (atomic_compare_exchange_weak(&address, &x, y)) dmb sy ldrex r0, [r3] cmp r0, r2 itt eq strexeq lr, r1, [r3] cmpeq.w lr, #0 dmb sy bne.n ... Since the programming guide to barrier instructions for ARM Cortex M4 states that: Omitting the DMB or DSB instruction in the

On core_cm4.h why is there casting like ((uint32_t)(int32_t)IRQn)?

廉价感情. 提交于 2019-12-01 09:22:45
In the following code from core_cm4.h why is there a double cast ((uint32_t)(int32_t)IRQn) ? For example in the following function: __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } What is the purpose of this? Since CM4 software implements negative interrupt sources for core, you have to cast value first to 32bit signed integer and later to unsigned 32bit to make proper right shift with padding zeros on the left side of number. CM4 uses -15 to -1 as CM4-Core sources and from 0 to

ARM Cortex-M compiler differences

大憨熊 提交于 2019-11-30 18:05:34
I'm about to develop some firmwares for Cortex-M cores on STM32 processors using C for my projects, and searching on the web I've found a lot of different compilers: Keil, IAR, Linaro, Yagarto and GNU Tools for ARM Embedded Processors . I was wondering, what functional differences are there between these compilers that might influence my choice? For example as an enthusiast I don't need support or assistance from the vendor, and a limitation on the code size is OK for the moment. Also the ease of use is not a main concern since I like to learn (and for the moment I have both Keil Lite and