addressing-mode

What does the following x86 assembler instruction do? call dword ptr ds:[00923030h] It's an indirect call I suspect, but exactly how does it compute the address to the call? [EDIT] Updated Whenever you see a memory operand that looks something like ds:0x00923030 , that's a segment-relative addressing mode. The actual address being referred tp is at linear address 0x00923030 relative to the base address of the ds segment register. Memory segmentation in the x86 architecture is somewhat confusing, and I think Wikipedia does a good job of explaining it. Basically, x86 has a number of special

I am using a CUDA texture in border addressing mode ( cudaAddressModeBorder ). I am reading texture coordinates using tex2D<float>() . When the texture coordinates fall outside the texture, tex2D<float>() returns 0 . How can I change this returned border value from 0 to something else? I could check the texture coordinate manually and set the border value myself. I was wondering if there was CUDA API where I can set such a border value. As mentioned by sgarizvi, CUDA supports only four, non-customizable address modes, namely, clamp , border , wrap and mirror , which are described in Section 3

What addressing mode is used in "mov cx, [bp+6]"? The processor is intel 8086. I am studying "Microprocessor and Interfacing" by Douglas V. Hall. I know its memory addressing mode. But not sure whether its based addressing mode or index addressing mode? [bp+6] is the based addressing mode. From the original 8086 docs: In based addressing, the effective address is the sum of a displacement value and the content of register BX or register BP. Indexed addressing mode is similar but with the SI or DI registers. Basically, you have the following modes: Direct memory accessing like [1234] . Register

To give a little bit of background, I wanted to study how x86 instructions are encoded/decoded manually. I came across the ModR/M and SIB bytes and it seems that understanding the x86 addressing modes is fundamental to understanding the instruction encoding scheme. Hence, I did a Google search for x86 addressing modes. Most blogs/videos that the search returned were addressing modes for the 8086 processor. Going through some of them, the different addressing modes were Register, Direct, Indirect, Indexed, Based , and some more. But the blogs use inconsistent names when referring to these

If one of my command lines says: jmp *0x804a180(,%eax,4) what does that mean? I ask specifically because there is no value before the first comma and I'm not sure exactly what the * before the address means. This instruction jumps to the location whose value is located at the address calculated as %eax * 4 + 0x804a180 . The * is used in AT&T syntax to indicate indirect jumps and calls. It basically means "jump to the location pointed to by this, instead of the value of this". It is useful to differentiate the following instructions: jmp myAddress # Jumps to the location myAddress jmp

I am trying to load the address of 'main' into a register (R10) in the GNU Assembler. I am unable to. Here I what I have and the error message I receive. main: lea main, %r10 I also tried the following syntax (this time using mov) main: movq $main, %r10 With both of the above I get the following error: /usr/bin/ld: /tmp/ccxZ8pWr.o: relocation R_X86_64_32S against symbol `main' can not be used when making a shared object; recompile with -fPIC /usr/bin/ld: final link failed: Nonrepresentable section on output collect2: error: ld returned 1 exit status Compiling with -fPIC does not resolve the

I see code like: mov ax, cs mov ds, ax mov es, ax Why can't I just compress this to: mov ds, cs mov es, cs Is the first way faster since its using the accumulator register? But that wouldn't seem intuitive since cs and ds are segment registers . Or is there some restriction that I'm unaware of? I'm using nasm by the way. You can't mov segment register to segment register -- there's no instruction for it. There is only so much room in a processor for the microcode for all its instructions. So one general instruction is often preferred over several special purpose ones for rarely uused