问题
Looking from this intel core i7 nehalem microarchitecure
It seems that each core has it's own private Register file. So I have a couple of short questions, because I thought that there is only 1 set of registers not dependent on number of cores.
- Does each core has its own private set of registers? (rax,rbx,rsp and so on.)
- Does each core has it's own MMU and TLB? not just one shared across all cores?
I know the questions are highly microarchitecture dependent but I think majority of modern x64 intel cpu's follow the same design principle.
回答1:
Each core has its own set of registers, MMU, TLB, level 1 caches (data and instruction), level 2 cache (this depends on processor) etc. Cache Coherency is supported across cores via "QPI" and in the case of high end Core 7 and server-based processors like Xeon, Cache Coherency is supported across processors on a multi-processor mother board by exposing "QPI" on the external pins of those processors (for processors where multi-processor cache coherency is not supported, "QPI" is not "exposed").
Wiki article: Nehalem
回答2:
Yes, each core has its set of registers. "Core" is equivalent of separate CPU on socket but with "multicore" the electronic wiring is simple.
来源：https://stackoverflow.com/questions/28815848/does-each-core-has-its-own-private-set-of-registers