the difference between a[b+1] and a[b+1'b1]

问题

when I try to write to a[b+1] where the bits of b are all '1' ,the value of the reg a[0] do not update,but when I try a[b+1'b1],it updated

  awaddr_wa              <= awaddr_wa + 2;
  awaddr[awaddr_wa]      <= AWADDR_M;
  awlen [awaddr_wa]      <= 4'd0;
  awaddr[awaddr_wa+6'd1] <= AWADDR_M+16;
  awlen [awaddr_wa+6'd1] <= 4'd0

so ,why?

回答1:

Here is a reproducible example:

module M;

  integer a[0:7] = {0,1,2,3,4,5,6,7};
  reg [2:0] b = -1;

  initial
    begin
      $display("a[b+1]=", a[b+1]);
      $display("a[b+1'b1]=", b+1'b1);
    end

endmodule

https://www.edaplayground.com/x/26Za

(Your question would be better had it included this)

You will see that the output is something like:

a[b+1]=          x 
a[b+1'b1]=0

1 is 32 bits wide. (All unbased literals in Verilog are 32 bits wide.)
When you mix bit widths like this in Verilog, Verilog must decide how many bits to use.
When you index an array out of range in Verilog this is not a catastrophe like it is in C. Instead the default value for the type of the array is returned. a is an array of integers, whose default value is 32'bx.
With a[b+1], Verilog will take the wider of 3 bits (b) and 32 bits (1), ie 32 bits. So, with b=3'b111, 1 is added to b using 32-bit arithmetic. In 32-bit arithmetic, 7+1 is 8, so a[b+1] is the same as a[8] which is out of range and hence 32'bx.
With a[b+1'b1], Verilog will take the wider of 3 bits (b) and 1 bit (1'b1), ie 3 bits. So, with b=3'b111, 1'b1 is added to b using 3-bit arithmetic. In 3-bit arithmetic, 7+1 is 0, so a[b+1'b1] is the same as a[0] which is not out of range and is 32'b0 in my example.

This is a classic trap in Verilog. It is an example of a Verilog self-determined expression. A self-determined expression is one where the number of bits used for the calculation depends only the widths of the operands. There are also context-determined expressions (eg F = A + B) where the number of bits also depends on the width of the variable (or net) being assigned to.

来源：https://stackoverflow.com/questions/57690004/the-difference-between-ab1-and-ab1b1

标签

verilog