FPGA_黑金AX301B_示例代码_001_LED

示例代码_001_LED

****************LED流水灯*************
`timescale 1ns/1ps
//=======================================
//模块声明
//========================================
module led(
    clk,    //the clock on the board -50MHz
    rst_n,  //reset botton
    led
);
//=======================================
//端口申明
//======================================
input clk;
input rst_n;
output [3:0] led;
//寄存器定义
reg [31:0] timer;
reg [3:0] led;
reg flag;
//=========================================
//LED
//=========================================
always@(posedge clk or negedge rst_n)
begin 
    if(~rst_n)
        led <= 4'b0001;
    else if(flag == 1)
        led = {led[0],led[3:1]};
    else 
        led <= led;
end
endmodule

来源：CSDN

作者：Hoalen

链接：https://blog.csdn.net/m0_37807173/article/details/104491558