Verilog: Non-integer parameters

问题

I have a parameter as follows:

parameter PARAM = 7'd69;

When I try to assign that value to the register below:

reg [6:0] r;

Like this:

r <= PARAM;

I get synthesis warnings:

Warning (10230): ... truncated value with size 32 to match size of target (7)

-

This I assume is because PARAM is being interpreted as an integer because it is defined as a parameter. Is there any way to define PARAM as 7 bits wide?

I could always pass this in as a 7 bit input to my module but I was wondering if there is a more elegant solution.

回答1:

You can define parameter as follow:

parameter [6:0]PARAM = 7'd69;

That way you're telling your compiler that PARAM size is 7 bits.

来源：https://stackoverflow.com/questions/18362402/verilog-non-integer-parameters