问题
When I read about MIPS architecture, I came across shadow registers which are said to be copies of general purpose registers.
I couldn't understand the following: When are shadow registers used?
回答1:
MIPS shadow registers are used to reduce register load/store overhead in handling interrupts. An interrupt to which a shadow register set is assigned does not need to save any of the existing context to provide free registers or load any interrupt-specific data stored in the shadow registers at entry to the interrupt handler; at exit of the interrupt handler no saving of the interrupt handler context or restoring of the previous context is necessary.
ARM provides a similar functionality with what it calls banked registers. (For ARM, only some of the GPRs are replicated.)
The MIPS Multithreading Application Specific Extension extends the use of shadow register sets to become thread contexts. (Shadow register sets in effect support a very limited form of switch-on-event-multithreading where the extra threads are conceptually limited to interrupt handlers and the events to interrupts.)
回答2:
I think you mean a mechanism which shares the result of the last stage of a pipeline to the previous stages executing the next instructions which may happen to read that result. There are no such shadow registers physically, just an intermediate selector for each previous stages which may need the result as an input bus which captures either from the register bank or from the result of the last stage. Sorry for my poor English phrasing.
来源：https://stackoverflow.com/questions/31422246/what-are-shadow-registers-in-mips-and-how-are-they-used