问题
I try to design a bch code as a shift register, so I have this schematic:
(clickable)
And I made a VHDL code in Altera Quartus to design this shift register with loops, the compilation works but it doesn't make the expected result during the simulation in ModelSim (no output). It may have some errors in my code:
-- Library declaration
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;
-- Entity declaration
ENTITY bchcode_implementation_top IS
PORT(clk : IN std_logic;
Q : OUT std_logic_vector(7 downto 0));
END bchcode_implementation_top;
-- Architecture declaration
ARCHITECTURE arch_bchcode_implementation_top OF bchcode_implementation_top IS
SIGNAL M: std_logic_vector(7 downto 0) := "10000000";
BEGIN
PROCESS(clk)
VARIABLE W: std_logic;
VARIABLE D: std_logic_vector(7 downto 0) := "00000000";
BEGIN
loop_bchcode: FOR I IN 7 TO 0 LOOP
IF rising_edge(clk) THEN
W := D(0) XOR M(I);
D(7) := W;
D(6) := D(7);
D(5) := D(6);
D(4) := D(5);
D(3) := D(4) XOR W;
D(2) := D(3);
D(1) := D(2) XOR W;
D(0) := D(1) XOR W;
END IF;
Q <= D;
END LOOP loop_bchcode;
END PROCESS;
END arch_bchcode_implementation_top;
If someone have an idea please.. thank you for your reponse.
回答1:
According to your code, I think you want to design the following schematic :
As I mentioned in the above comment, if you want to use variables (instead of signals), you must change the order of assignments.
Also the range of loop must be 7 DOWNTO 0 (instead of 7 TO 0).
The output is ready after 1 cycle. If you want to do the operation in 8 cycles, you must use a counter that is incremented on each clock rising edge. (instead of using for loop)
I edited your code with the above changes and simulated it with Modelsim 10.3. I could get the correct result on the first clock rising edge :
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
-- Entity declaration
ENTITY bchcode_implementation_top IS
PORT(
clk : IN std_logic;
Q : OUT std_logic_vector(7 DOWNTO 0)
);
END bchcode_implementation_top;
-- Architecture declaration
ARCHITECTURE arch_bchcode_implementation_top OF bchcode_implementation_top IS
SIGNAL M : std_logic_vector(7 DOWNTO 0) := "10000000";
BEGIN
PROCESS(clk)
VARIABLE I : integer;
VARIABLE W : std_logic;
VARIABLE D : std_logic_vector(7 DOWNTO 0) := "00000000";
BEGIN
loop_bchcode: FOR I IN 7 DOWNTO 0 LOOP
IF rising_edge(clk) THEN
W := D(0) XOR M(I);
D(0) := D(1) XOR W;
D(1) := D(2) XOR W;
D(2) := D(3);
D(3) := D(4) XOR W;
D(4) := D(5);
D(5) := D(6);
D(6) := D(7);
D(7) := W;
END IF;
END LOOP loop_bchcode;
Q <= D;
END PROCESS;
END arch_bchcode_implementation_top;
回答2:
I finally fix the problem, here is my code to describe a shift register for bch code (15,7), thank you Amir for your help.
-- Library declaration
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
-- Entity declaration
ENTITY bchcode_implementation_top IS
PORT(clk, rst : IN std_logic;
Din : IN std_logic_vector(7 downto 0);
Dout : BUFFER std_logic_vector(7 downto 0)); -- OUT port cannot be read back to the design
END bchcode_implementation_top;
-- Architecture declaration
ARCHITECTURE arch_bchcode_implementation_top OF bchcode_implementation_top IS
SIGNAL count : std_logic_vector(7 downto 0);
BEGIN
PROCESS(clk, rst, Din)
VARIABLE I : integer := 7;
BEGIN
count <= Din;
IF rst = '1' THEN
Dout <= "00000000";
ELSE
IF rising_edge(clk) THEN
Dout(0) <= Dout(1) XOR (Dout(0) XOR count(I));
Dout(1) <= Dout(2) XOR (Dout(0) XOR count(I));
Dout(2) <= Dout(3);
Dout(3) <= Dout(4) XOR (Dout(0) XOR count(I));
Dout(4) <= Dout(5);
Dout(5) <= Dout(6);
Dout(6) <= Dout(7);
Dout(7) <= Dout(0) XOR count(I);
I := I - 1;
END IF;
END IF;
END PROCESS;
END arch_bchcode_implementation_top;
来源：https://stackoverflow.com/questions/29840819/design-a-shift-register-in-vhdl