Makefile and variable target from command line

问题

Newbie question for Makefiles... why doesn't this work?

TARGET=$@

$(TARGET): * **/*
    @echo "TARGET=$(TARGET)"

Where this does?

TARGET=my_target

$(TARGET): * **/*
    @echo "TARGET=$(TARGET)"

When started with make my_target?

Result of the former is, "no rule to make target `my_target'."

In addition to the question "why this doesn't work," is there a workaround? I'd like to be able to specify an arbitrary target from the command line. I suppose I could react to an env var, but that makes the CLI clunky, e.g., make target=my_target build or similar.

I've searched, but I'm not getting the right hits to solve this. GNU make 3.81. Thanks!

回答1:

The automatic variable $@ is defined in the context of a pattern rule; outside of any rule it has no value.

If you want Make to do the same thing to whatever target you name, you can use a match-anything rule:

%:
    @echo TARGET=$@

来源：https://stackoverflow.com/questions/50751346/makefile-and-variable-target-from-command-line