VHDL Error (10818): Can't infer register

问题

So I am a beginner in VHDL and I am trying to code a MIPS processor for a FPGA. The file for the CPU Register is not compiling. It is generating an error code as following Error (10818): Can't infer register for "Reg[0][2]" at cpu_register.vhd(32) because it does not hold its value outside the clock edge

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cpu_register is
Port ( Source_Register_Address : in std_logic_vector(4 downto 0);
 Target_Register_Address : in std_logic_vector(4 downto 0);
 Destination_Register_Address : in std_logic_vector(4 downto 0);
 Cyclic_Target_Register_Address : in std_logic_vector(4 downto 0);
 Program_Counter : in std_logic_vector(31 downto 0);
 Load_Data : in std_logic_vector(31 downto 0);
 Execution_Result : in std_logic_vector(31 downto 0);
 Operation_Code : in std_logic_vector(5 downto 0);
 Source_Register_Data : out std_logic_vector(31 downto 0);
 Target_Register_Data : out std_logic_vector(31 downto 0);
 Clock : in std_logic);
end cpu_register;
architecture behavioral of cpu_register is
type Register_Array is array (0 to 31) of std_logic_vector(31 downto 0);
signal Reg: Register_Array;
begin
t1:process
(Operation_Code,Source_Register_Address,Target_Register_Address,Clock)
begin
Reg(0) <= "00000000000000000000000000000000";
Source_Register_Data <= Reg(CONV_INTEGER(Source_Register_Address));
Target_Register_Data <= Reg(CONV_INTEGER(Target_Register_Address));
end process;
t2: process (Clock)
begin
Reg(0) <= "00000000000000000000000000000000";
if (Clock'event and Clock='0') then
case Operation_Code is
when "000000" =>
if (Destination_Register_Address="00000") then
Reg(0) <= "00000000000000000000000000000000";
else
Reg(CONV_INTEGER(Destination_Register_Address)) <=
Execution_Result;
end if;
when "001000" | "001001" | "001100" | "001101" | "001110" | "001111" |
"001010" | "001011" =>
if (Cyclic_Target_Register_Address="00000") then
Reg(0) <= "00000000000000000000000000000000";
else
Reg(CONV_INTEGER(Cyclic_Target_Register_Address)) <= Execution_Result;
end if;
when "100011" =>
if (Cyclic_Target_Register_Address="00000") then
Reg(0) <= "00000000000000000000000000000000";
else
Reg(CONV_INTEGER(Cyclic_Target_Register_Address)) <= Load_Data;
end if;
when "000011" =>
Reg(31) <= Program_Counter;
when others =>
Reg(0) <= "00000000000000000000000000000000";
end case;
end if;
end process;
end behavioral;

Any help on how to fix it would be much appreciated. Thanks

回答1:

Comment out the two Reg(0) assignments outside the if statement conditioned by clock'event and clock = '0'.

The assignment in t1 looks unintentional and can cause 'X's during simulation. You'd expect your synthesis software might complain as well.

t1:process
(Operation_Code,Source_Register_Address,Target_Register_Address,Clock)
begin
-- Reg(0) <= "00000000000000000000000000000000";
Source_Register_Data <= Reg(CONV_INTEGER(Source_Register_Address));
Target_Register_Data <= Reg(CONV_INTEGER(Target_Register_Address));
end process;
t2: 
    process (Clock)
    begin
        -- Reg(0) <= "00000000000000000000000000000000";
        if Clock'event and Clock ='0' then
            case Operation_Code is
            when "000000" =>
                if (Destination_Register_Address="00000") then
                    Reg(0) <= "00000000000000000000000000000000";
                else
                    Reg(CONV_INTEGER(Destination_Register_Address)) <=
                            Execution_Result;
                end if;
            when "001000" | "001001" | "001100" | 
                 "001101" | "001110" | "001111" |
                 "001010" | "001011" =>
                if (Cyclic_Target_Register_Address="00000") then
                    Reg(0) <= "00000000000000000000000000000000";
                else
                    Reg(CONV_INTEGER(Cyclic_Target_Register_Address)) <= 
                             Execution_Result;
                end if;
            when "100011" =>
                if (Cyclic_Target_Register_Address="00000") then
                    Reg(0) <= "00000000000000000000000000000000";
                else
                    Reg(CONV_INTEGER(Cyclic_Target_Register_Address)) <= 
                            Load_Data;
                end if;
            when "000011" =>
                Reg(31) <= Program_Counter;
            when others =>
                Reg(0) <= "00000000000000000000000000000000";
            end case;
        end if;
    end process;

The one commented out in t2 is causing your error.

来源：https://stackoverflow.com/questions/33907580/vhdl-error-10818-cant-infer-register