问题
I am working on a project to facilitate verilog programming by using perl scripting language. Now I want to write a script to scan a top verilog file, and then generate the hierarchy list for the module, which suggests that I need to extract the module instantiation statement from the verilog file, here is the problem:
How to write a regular expression to match the module instantiation in a verilog file, since we need to know the submodule names of the top module file.
回答1:
The SYNOPSYS of Verilog::Netlist shows how to read in a Verilog file and find modules throughout the hierarchy. Although you could use regular expressions in some limited cases, it would be worthwhile to use this CPAN parser module in the long run.
Here is some example code I posted on PerlMonks a while back: verilog perl usage (Verilog::Netlist)
The vhier script which is part of the Verilog-Perl distribution is also handy.
来源：https://stackoverflow.com/questions/9066483/how-do-i-write-a-regex-to-match-the-module-instantiation-in-a-verilog-file