Makefile: Passing command line arguments to file inside Makefile

问题

Inside my Makfile I have the following,

smktestrun: smktest
    @../projects/test.sh

And I call this using:

Make smktestrun

But sometimes I need to pass an parameter/argument along with this file (test.sh)

So basically I would like:

test.sh -abc

But if i just pass the argument in the Makefile itself, the argument is not taken as simply the sheel script is executed.

So is there a way I could specify in the Makefile that an argument needs to be passed with that file?

Thanks.

回答1:

Something like

smktestrun: smktest
        @../projects/test.sh $(TESTARGS)

Then call the Makefile with

$ make smktestrun TESTARGS="-abc"

回答2:

You could define a variable in Makefile.

smktestrun: smktest
    @../projects/test.sh ${ARG}

Then the command line of make is:

make smktestrun ARG="something"

来源：https://stackoverflow.com/questions/15500204/makefile-passing-command-line-arguments-to-file-inside-makefile