What does “rep; nop;” mean in x86 assembly? Is it the same as the “pause” instruction?

Question

• What does rep; nop mean?
• Is it the same as pause instruction?
• Is it the same as rep nop (without the semi-colon)?
• What's the difference to the simple nop instruction?
• Does it behave differently on AMD and Intel processors?
• (bonus) Where is the official documentation for these instructions?

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Motivation for this question

After some discussion in the comments of another question, I realized that I don't know what rep; nop; means in x86 (or x86-64) assembly. And also I couldn't find a good explanation on the web.

I know that rep is a prefix that means "repeat the next instruction cx times" (or at least it was, in old 16-bit x86 assembly). According to this summary table at Wikipedia, it seems rep can only be used with movs, stos, cmps, lods, scas (but maybe this limitation was removed on newer processors). Thus, I would think rep nop (without semi-colon) would repeat a nop operation cx times.

However, after further searching, I got even more confused. It seems that rep; nop and pause map to the exactly same opcode, and pause has a bit different behavior than just nop. Some old mail from 2005 said different things:

• "try not to burn too much power"
• "it is equivalent to 'nop' just with 2 byte encoding."
• "it is magic on intel. Its like 'nop but let the other HT sibling run'"
• "it is pause on intel and fast padding on Athlon"

With these different opinions, I couldn't understand the correct meaning.

It's being used in Linux kernel (on both i386 and x86_64), together with this comment: /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ It is also being used in BeRTOS, with the same comment.

Answer 1

rep; nop is indeed the same as the pause instruction (opcode F390). It might be used for assemblers which don't support the pause instruction yet. On previous processors, this simply did nothing, just like nop but in two bytes. On new processors which support hyperthreading, it is used as a hint to the processor that you are executing a spinloop to increase performance. From Intel's instruction reference:

Improves the performance of spin-wait loops. When executing a “spin-wait loop,” a Pentium 4 or Intel Xeon processor suffers a severe performance penalty when exiting the loop because it detects a possible memory order violation. The PAUSE instruction provides a hint to the processor that the code sequence is a spin-wait loop. The processor uses this hint to avoid the memory order violation in most situations, which greatly improves processor performance. For this reason, it is recommended that a PAUSE instruction be placed in all spin-wait loops.

Answer 2

Prefixes that don't apply to an instruction are ignored. However, future CPUs can use that byte sequence to encode a new instruction. (yes, the x86 opcode space is so limited that they do crazy stuff like this, and yes it makes the decoders complicated.)

In this case, it means you can use pause in spinloops without breaking backwards compat. Old CPUs that don't know about pause will decode it as a NOP with no harm done. On new CPUs, you get the benefit of power-saving / HT friendliness, and avoiding memory-ordering mis-speculation when the memory you're spinning on does change and you're leaving the spin loop.

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Links to Intel's manuals and tons of other good stuff on the x86 tag wiki info page: https://stackoverflow.com/tags/x86/info

Another case of a meaningless rep prefix becoming a new instruction on new CPUs: lzcnt is F3 0F BD /r. On CPUs that don't support that instruction (missing the LZCNT feature flag in their CPUID), it decodes as rep bsr, which runs the same as bsr. So on old CPUs, it produces 32 - expected_result, and is undefined when the input was zero.

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One case of a meaningless rep prefix that will probably never decode differently: rep ret is used by default by gcc when targeting "generic" CPUs (i.e. not targetting a specific CPU with -march or -mtune, and not targetting AMD K8 or K10.) It will be decades before anyone could make a CPU that decodes rep ret as anything other than ret, because it's present in most binaries in most Linux distros. See What does `rep ret` mean?