Why this Modelsim error? “Ambiguous types in signal assignment statement.”

问题

I am trying to compile the following example with ModelSim Microsemi 10.2c:

architecture example of assignment_to_an_aggregate is
    type vowel_type is (a, e, i, o, u);
    type consonant_type is (b, c, d, f, g);

    signal my_vowel: vowel_type;
    signal my_consonant: consonant_type;
begin

    (my_vowel, my_consonant) <= (a, b);

end;

And it gives the following error:

** Error: assignment_to_aggregates.vhdl(40): (vcom-1349) Ambiguous types in signal assignment statement.

   Possible target types are:
        std.STANDARD.TIME_VECTOR
        std.STANDARD.REAL_VECTOR
        std.STANDARD.INTEGER_VECTOR
        std.STANDARD.BIT_VECTOR
        std.STANDARD.BOOLEAN_VECTOR
        std.STANDARD.STRING

** Error: assignment_to_aggregates.vhdl(57): VHDL Compiler exiting

Anyone could explain whit this doesn't work? And why would the compiler think that TIME_VECTOR, STRING, etc. are reasonable types for the target of this assignment? Note: I get the same error even when the target aggregate has only signals of a same type.

Thanks!

回答1:

While I can't comment on Modelsim's peculiarities of type messages, the problem is the type of the right hand side aggregate can't be discerned from the context.

Try:

entity assignment_to_an_aggregate is
end entity;
architecture example of assignment_to_an_aggregate is
    type vowel_type is (a, e, i, o, u);
    type consonant_type is (b, c, d, f, g);

    type vowel_consonant is 
        record 
            vowel: vowel_type;
            consonant: consonant_type; 
        end record;

    signal my_vowel: vowel_type;
    signal my_consonant: consonant_type;
begin

    (my_vowel, my_consonant) <= vowel_consonant'(a,b);

end;

And you'll note that the left hand side aggregate depends on the right hand side expression for it's type.

(And a type declaration bears no simulation nor synthesis overhead burden, and no where is there a named object declared as a record type).

Ok, so if I understand correctly, then everything that appears on the right hand side of an assignment needs to have a explicitly defined type? Or to put it another way, every aggregate must have a defined type? – VHDL Addict 5 mins ago

No. In this case the target of a signal assignment is an aggregate:

IEEE Std 1076-1993, 8.4 Signal assignment statement (-2008, 10.5/10.5.2.1):

If the target of the signal assignment statement is in the form of an aggregate, then the type of the aggregate must be determinable from the context, excluding the aggregate itself but including the fact that the type of the aggregate must be a composite type.

What else is there for context besides the right hand side? You can't make the aggregate on the left hand side a qualified expression. The target of a signal assignment must be named and the expression has no name.

The Modelsim error message you got didn't specify which side of the assignment statement it was complaining about while some other tool might be more enlightening:

assignment_to_aggregate.vhdl:23:19: type of waveform is unknown, use type qualifier

You ever notice error messages are intended for someone who doesn't need them?

来源：https://stackoverflow.com/questions/23503891/why-this-modelsim-error-ambiguous-types-in-signal-assignment-statement

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variable-assignment

vhdl

aggregate