VHDL: Is it possible to define a generic type with records?

问题

I am trying to define a complex type (i.e, a type that consists of both a real and imaginary part) and am trying to find out a way to make it generic.

This my current static code:

  type complex_vector is record
    Re : signed(15 downto 0);
    Im : signed(15 downto 0);
  end record;

Now I wonder whether there is a way to make this generic, in in other word something like:

  type complex_vector (Generic: Integer := WIDTH) is record
    Re : signed(WIDTH downto 0);
    Im : signed(WIDTH downto 0);
  end record;

I tried to google for a solution as well as going through my books, but I cannot find any solution. Is there really none? Without records it is possible to wright something like this:

type blaaa is array (NATURAL range <>) of STD_LOGIC;

Thanks for any input

EDIT:

Or could I do something like the following?

type complex_primitives is (re, im);
type complex_vector is array (re to im) of signed(natural range <>);

The compiler complains though..

回答1:

The following is legal syntax in VHDL-2008:

type complex is record
  re : signed ;  -- Note that this is unconstrained
  im : signed ;
end record ;

signal my_complex_signal : complex (re(7 downto 0), im(7 downto 0)) ;

IMPORTANT NOTE This example makes use of records with unconstrained arrays. Support for VHDL-2008 at this point is hit-and-miss. Some tools support many of VHDL-2008 features, but many do not yet fully support all new features.

To read about VHDL-2008 and the new features, see this presentation which is a good summary on the subject.

回答2:

Until VHDL-2008 is supported (don't hold your breath!) there are is a sub-optimal fudge...

Create the different sized records you want in multiple packages of the same name and then optionally compile in the package defining the width you want to use.

-- complex_vector_16.vhd
package types is
  type complex_vector is record
    Re : signed(15 downto 0);
    Im : signed(15 downto 0);
  end record;
end;

-- complex_vector_32.vhd
package types is
  type complex_vector is record
    Re : signed(31 downto 0);
    Im : signed(31 downto 0);
  end record;
end;


library complex.types
use complex.types.complex_vector;

The severe limitation of this method is that you can only support a single form of complex_vector in the design, but on the plus side you don't have to worry about tool support!

It would be useful to raise a support/enhancement request with every vendor in your toolchain regarding your use case. The more they get bugged the sooner VHDL-2008 will be supported.

来源：https://stackoverflow.com/questions/6356657/vhdl-is-it-possible-to-define-a-generic-type-with-records

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