问题
I have to write a program that changes an LED sequence at each clock pulse for one sequence.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity REG_LED is
PORT(CLK: IN std_logic; -- CLK input
LEDS: Out std_logic_vector (4 downto 0):= "11111"); -- initialise output
End REG_LED;
ARCHITECTURE behavioral OF REG_LED IS
SIGNAL Temp: std_logic_vector (3 downto 0):= "0000"; -- initailise comparison signal
BEGIN
CLK_Process: PROCESS (CLK) -- begin
BEGIN
if rising_edge(CLK) Then
Temp <= Temp + 1 ;
END IF;
iF TEMP > "1000" THEN
Temp <= "XXXX";
End IF;
END PROCESS ;
LED_PROCESS: Process (Temp) --
BEGIN
Case Temp is
When "0000" =>
LEDS <= "11111";
When "0001" =>
LEDS <= "00001";
When "0010" =>
LEDS <= "00001";
When "0011" =>
LEDS <= "11111";
When "0100" =>
LEDS <= "00000";
When "0101" =>
LEDS <= "11111";
When "0110" =>
LEDS <= "00100";
When "0111" =>
LEDS <= "01010";
When "1000" =>
LEDS <= "10001";
When others =>
LEDS <= "10001";
End Case;
End Process;
END behavioral;
Does this look more like what you would expect? it simulates but i cant test the synthesis of the code as i have now hardware to test it with. Or if there is a way because I'm new to VHDL I haven't worked out how to test it.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity REG_LED is
PORT(CLK: IN std_logic; -- CLK input
LEDS: Out std_logic_vector (4 downto 0):= "11111"); -- initialise output
End REG_LED;
ARCHITECTURE behavioral OF REG_LED IS
SIGNAL Temp: integer range 0 to 9:= 0; -- initailise comparison signal
BEGIN
CLK_Process: PROCESS (CLK) -- begin
BEGIN
if rising_edge(CLK) Then
if Temp = 8 then
Temp <= 0; -- State Count Reset
else
Temp <= Temp + 1 ; -- State Count
End if;
END IF;
END PROCESS ;
LED_PROCESS: Process (Temp) -- LED Outputs based on Temp count
BEGIN
Case Temp is
When 0 =>
LEDS <= "11111"; -- S0
When 1 =>
LEDS <= "00001"; -- S1
When 2 =>
LEDS <= "00001"; -- S2
When 3 =>
LEDS <= "11111"; -- S3
When 4 =>
LEDS <= "00000"; -- S4
When 5 =>
LEDS <= "11111"; -- S5
When 6 =>
LEDS <= "00100"; -- S6
When 7 =>
LEDS <= "01010"; -- S7
When 8 =>
LEDS <= "10001"; -- S8
When others =>
LEDS <= "11111"; -- Restart Sequence
End Case;
End Process;
回答1:
This code is pretty good, but here is one thing that needs attention:
You don't both these packages:
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
In fact, your code is only using the std_logic_unsigned package; it is not making use of the numeric_std package at all. The std_logic_unsigned package defines various arithmetic operators for the std_logic_vector type. These assume unsigned arithmetic, hence the name. You are making use of the std_logic_unsigned package in this line:
Temp <= Temp + 1 ;
For new code, you should really use the numeric_std package, not the std_logic_unsigned package. To do this, you would have to change the type of Temp to unsigned. Type unsigned is just an array of std_logic like std_logic_vector, but as its name implies, it is used to implement unsigned arithmetic.
So, I would
i) delete this line:
use ieee.std_logic_unsigned.all;
ii) change this line:
SIGNAL Temp: std_logic_vector (3 downto 0):= "0000"; -- initailise comparison signal
to:
SIGNAL Temp: unsigned (3 downto 0):= "0000"; -- initailise comparison signal
iii) (as Scary Jeff points out) think about what the assignment of Temp to "XXXX" is doing. Wouldn't you prefer your counter to wrap round to "0000"? If, if you want it to freeze at "1000", you'll need some different code. In any case, never put any code outside the test for the rising_edge of clock. (It doesn't comply with the template I showed you. What logic would you expect to be produced by this code?)
来源：https://stackoverflow.com/questions/40130851/vhdl-clocked-led-sequence-part-2