How to include time delay in synthesized verilog?

问题

I am trying to write a synthesizable code in verilog, in which I require to include a time delay of few seconds. I have done the simulation using #delay, but this is not acceptable by synthesizer.

In the process of synthesizing a FSM, which change its states not based on some condition but after few seconds of time delay, I want the above time delay method. FSM has to switch states say from state_1 to state_2 after 4 seconds and state_2 to state_3 after 2 seconds and so on.

回答1:

For switching the states after a time delay,I hope this code helps.

current_state=state_1;
for(i=0;i<=timedelay*freq;i=i+1)
@posedge;
current_state=state_2;

回答2:

If you know your clock frequency is x Hz, and you want to wait y seconds, then simply use a counter and wait until you reach the number x*y.

e.g. for a clock of 1kHz and a delay of 3 seconds this code will trigger do_something after the time delay.

`define CLOCK_FREQ 1000
`define TIME_DELAY 3

reg [31:0] count=0;

assign do_something = (count==`CLOCK_FREQ*`TIME_DELAY);

always @(posedge clk)
begin
   count <= count + 1'b1;
end

来源：https://stackoverflow.com/questions/17361606/how-to-include-time-delay-in-synthesized-verilog