问题
Synthesizable register(s) can conventionally be verified using access technique that use address & data buses (these buses are very much part of the actual hardware present on the silicon chip). But this conventional access technique consumes finite time.
Register Abstraction Layer (RAL) with UVM is a very efficient way of verifying RTL registers in your design. One of the key features of this methodology is 'backdoor access', by virtue of which one can access (i.e. read from or write into) any RTL register(s) in zero simulation time. The backdoor access mechanism uses hierarchical HDL paths to do so.
The question is what physical provisions on the silicon makes this, access-in-zero-time, possible?
回答1:
You don't use any special physical provisions on silicon to enable backdoor access. UVM is used with simulation and in simulation you can have access to the values of any signal in the design. At most, a designer could create some throw away signal for you to collect bits of a register that are scattered throughout the design.
回答2:
The Register Abstraction Layer in the UVM provides backdoor access to registers using techniques only available during simulation. This could be through hierarchical references not allowed by synthesis tools, or using a tool programming interface like the the DPI. So backdoor here refers to a simulation tool's ability to modify the state of the design.
There is, of course, backdoors in design that circumvent the normal hardware protocol for accessing registers, but that is a functional aspect of the design and would never occur in 0 time. A scan chain would be an example of backdoor hardware access.
回答3:
None, obviously. Zero access time is physically impossible. You should verify your design before committing it to silicon.
来源：https://stackoverflow.com/questions/32454818/how-is-backdoor-access-for-registers-physically-implemented-in-a-vlsi-design