What is need of Assign/Deassign in Verilog?

Question

I am here giving here 2 Verilog modules, which during simulation behaves same. But I don't understand that why to use assign/deassign in these modules, i.e. what is the difference between these 2 codes?

// Code 1 - Without assign-deassign
module dff (q,qbar,clk,reset,d)
  input clk, reset, d;
  output reg q, qbar;

  always @ (posedge reset, negedge clk)
  begin
    if(reset)
    begin
      q=1;
      qbar=0;
    end
    else
    begin
      q=d;
      qbar=~d;
    end
  end
endmodule

// Code 2 - With assign-deassign
module dff (q,qbar,clk,reset,d)
  input clk, reset, d;
  output reg q, qbar;

  always @ (negedge clk)
  begin
    q=d;
    qbar=~d;
  end

  always @ (reset)
  begin
    if(reset)
    begin
      assign q=1;
      assign qbar=0;
    end
    else
    begin
      deassign q;
      deassign qbar;
    end
  end
endmodule

Answer 1

The original purpose of the procedural assign/deassign statements in your example was to separate synchronous logic from asynchronous logic in two distinct processes. It's also more efficient for simulation because the synchronous block does not have to check the reset signal every clock cycle. Modeling latches is also more efficient for simulation because because you don't have to check the enable signal every time the data changes, only when the latch is open.

This construct was synthesizable by early synthesis tools, but unfortunately, the big synthesis vendor decided not to support it, so no one uses these procedural constructs anymore.

Answer 2

The statements without assign are within a @ edge block, and are evaluated only at that edge. assign describes combinatorial continuous logic, and is by definition sensitive to its inputs.

In Code 1, q will change only when clk or reset changes, not when d changes.

Code 2 has the effect that when reset is asserted, this block will continuously drive q=1 (conflicting with any other driver) but when reset is negated, it will stop driving q.

This is actually more unusual use perhaps of assign - within an @edge block.

More conventional use would be like

assign out = (enable) ? data : 1'bz; 

which will change whenever either enable or data changes.