Chisel3: Partial assignment to a multi-bit slice of a Vector IO

佐手、 提交于 2019-12-06 08:16:55

I don't think there is a way to do this currently in chisel. Using slice on the LHS means that the collection returned by splice is not something that supports a connect method. That being said, the following seems to work, though I haven't considered into all the implications of it.

class Slicer extends Module {
  implicit class SeqHelper(val seq: Seq[Bits]) {
    /**
      * Promotes a Seq of Bits to a class that supports the connect operator
      */
    def := (other: Seq[Bits]): Unit = {
      seq.zip(other).foreach { case (a, b) => a := b}
    } 
  }

  val io = IO(new Bundle {
    val in1  = Input(Vec(4, Bool()))
    val out1 = Output(Vec(4, Bool()))
  })

  io.out1.slice(0, 2) := io.in1.slice(0, 2)
}

You could put the SlicerHelper in a package object making it generally accessible. Less exotic idioms to consider might be.

io.out1.slice(0, 2).zip(io.in1.slice(0, 2)).foreach { case (a, b) => a:= b }

or

io.out1.zip(io.in1).slice(0, 2).foreach { case (a, b) => a:= b }
标签
易学教程内所有资源均来自网络或用户发布的内容,如有违反法律规定的内容欢迎反馈
该文章没有解决你所遇到的问题?点击提问,说说你的问题,让更多的人一起探讨吧!