stp aarch64 instruction must be used with “non-contiguous pair of registers”

Question

The aarch64 architecture doesn't have instructions for multiple store and load, i.e. there are no equivalents of stm and ldm from armv7 arch. Instead you must use the stp and ldp instructions for store and loading pairs of registers.

Accroding to the ARM reference manual:

http://www.element14.com/community/servlet/JiveServlet/previewBody/41836-102-1-229511/ARM.Reference_Manual.pdf

There are no multiple register LDM, STM, PUSH and POP instructions, but load-store of a non-> contiguous pair of registers is available.

My question is, what does non-contiguous mean or refer to here? My instant reaction was that it means you can't use consecutively numbered registers with these commands, e.g.

stp x0, x1, [sp, #-16]!

is illegal. However I don't believe this is the case. I've seen example code doing exactly this and furthermore I've managed to get (Apple's) Clang to generate similar code, e.g.

stp x1, x0, [fp, #-16]!

I can't for the life of me think what contiguous then means. I thought it could be something to do with using overlapping registers, e.g.

stp x0, x0, [sp, #-16]!
stp w0, x0, [sp, #-12]!

However I've seen example code doing this sort of things as well (not to say that code was correct!). Also I would have explicitly used the terminology overlapping rather than contiguous if this were the case.

Any ideas?

Answer 1

It is primarily highlighting the contrast with the A32 (ARM) LDRD/STRD instructions*, which can only load a consecutive pair of registers, the lowest of which must be even-numbered, i.e.:

LDRD r0, r1, [sp]   @ OK
LDRD r0, r7, [sp]   @ <Rt> and <Rt2> are non-contiguous: invalid
LDRD r3, r4, [sp]   @ Contiguous but <Rt> odd-numbered: invalid

[This is down to the fact that there's only space to encode one target register in the instruction, so the architecture must have a defined way of inferring the second target register.]

In contrast, the A64 LDP/STP encodings have room to encode two target registers, which means they can be any two registers in any order, i.e. they are allowed to be non-contiguous - it's a permission, not a restriction.

Note that that particular document is obsolete since the release of the full ARMv8 ARM, which has proper detailed instruction pages that should be slightly less ambiguous.

_{* The T32 (Thumb) encodings don't have this restriction, since the lack of a condition predicate means there's space to encode the second target register, much like A64.}