Conditional instantiation of verilog module

问题

Is it possible to instantiate a module conditionally in verliog ?

example :

if (en==1)  
  then module1 instantiation  
else  
  module2 instantiation

回答1:

From IEEE Std 1364-2001 :

12.1.3.3 generate-conditional A generate-conditional is an if-else-if generate construct that permits modules, user defined primitives, Verilog gate primitives, continuous assignments, initial blocks and always blocks to be conditionally instantiated into another module based on an expression that is deterministic at the time the design is elaborated.

example given in LRM :

module multiplier(a,b,product);
parameter a_width = 8, b_width = 8;
localparam product_width = a_width+b_width; // can not be modified
// directly with the defparam statement
// or the module instance statement #
input [a_width-1:0] a;
input [b_width-1:0] b;
output [product_width-1:0] product;

generate
    if((a_width < 8) || (b_width < 8))
        CLA_multiplier #(a_width,b_width) u1(a, b, product);
        // instantiate a CLA multiplier
    else
        WALLACE_multiplier #(a_width,b_width) u1(a, b, product);
        // instantiate a Wallace-tree multiplier
endgenerate
// The generated instance name is u1

endmodule

回答2:

You can use compiler directives like

`define FOO
`ifdef FOO
    module1 ...
`else
    module2 ...
`endif

to choose an instantiation at compile time.

If in you are asking if you can instantiate a module based on a wire value, no you cannot do that.

回答3:

You can not do this at runtime as you are describing hardware, which can not be changed on the fly. You may enable or disable a feature to save power but you can not make it stop existing. Assuming you are looking to improve the reuse or configure-ability of blocks:

Pre compiler techniques are often used as well as the ``defines` (tick defines) Tim mentions.

They would consist of a Perl, ruby etc script which parses a template file.

My Previous answer using ruby scripts and templates.

来源：https://stackoverflow.com/questions/15240591/conditional-instantiation-of-verilog-module

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conditional

instantiation

verilog

hdl