x86-64

x86 32 bit opcodes that differ in x86-x64 or entirely removed

∥☆過路亽.° 提交于 2019-11-30 13:03:03
问题 I've looked up Wikipedia for x86 backward compatibility in x86-x64 and it says: x86-64 is fully backwards compatible with 16-bit and 32-bit x86 code.Because the full x86 16-bit and 32-bit instruction sets remain implemented in hardware without any intervening emulation, existing x86 executables run with no compatibility or performance penalties,whereas existing applications that are recoded to take advantage of new features of the processor design may achieve performance improvements. So I've

what does the cmpq instruction do?

大兔子大兔子 提交于 2019-11-30 12:35:41
I was reading the following definition for syscall: .text .globl syscall .type syscall,%function .align 16 syscall: movq %rdi, %rax /* Syscall number -> rax. */ movq %rsi, %rdi /* shift arg1 - arg5. */ movq %rdx, %rsi movq %rcx, %rdx movq %r8, %r10 movq %r9, %r8 movq 8(%rsp),%r9 /* arg6 is on the stack. */ syscall /* Do the system call. */ cmpq $-4095, %rax /* Check %rax for error. */ jae __syscall_error /* Branch forward if it failed. */ ret /* Return to caller. */ .size syscall,.-syscall I saw it explained that the line cmpq $-4095 %rax determines whether %rax contains a value between -1 and

Are atomic variables lock-free?

孤人 提交于 2019-11-30 12:01:44
问题 When we talk about atomic variables, such as C++11's atomic<> , is it lock free? Or is lock-freeness something different? If I manage a queue with atomic variables, will it be slower than a lock-free queue? 回答1: The standard does not specify if atomic objects are lock-free. On a platform that doesn't provide lock-free atomic operations for a type T, atomic<T> objects may be implemented using a mutex, which wouldn't be lock-free. In that case, any containers using these objects in their

What are .seh_* assembly commands that gcc outputs?

試著忘記壹切 提交于 2019-11-30 11:43:45
I use gcc -S for a hello world program. What are the 5 .seh_ commands? I can't seem to find much info at all about them when I search. .file "hi.c" .def __main; .scl 2; .type 32; .endef .section .rdata,"dr" .LC0: .ascii "Hello World\0" .text .globl main .def main; .scl 2; .type 32; .endef .seh_proc main main: pushq %rbp .seh_pushreg %rbp movq %rsp, %rbp .seh_setframe %rbp, 0 subq $32, %rsp .seh_stackalloc 32 .seh_endprologue call __main leaq .LC0(%rip), %rcx call puts movl $0, %eax addq $32, %rsp popq %rbp ret .seh_endproc .ident "GCC: (rubenvb-4.8.0) 4.8.0" .def puts; .scl 2; .type 32; .endef

Why isn't the text colored when using the 0Eh 10h interrupt?

随声附和 提交于 2019-11-30 09:57:10
问题 I'm using the 10h interrupt with AH as 0Eh to output "Hello World!" The text is ouputted but its not colored. I'm running it on qemu-system-x86_64, assembling with NASM, and my code is as follows: BITS 16 start: mov ax, 07C0h ; Set up 4K stack space after this bootloader add ax, 288 ; (4096 + 512) / 16 bytes per paragraph mov ss, ax mov sp, 4096 mov ax, 07C0h ; Set data segment to where we're loaded mov ds, ax mov si, text_string ; Put string position into SI call print_string ; Call our

Creating a proper Task State Segment (TSS) structure with and without an IO Bitmap?

≡放荡痞女 提交于 2019-11-30 09:26:25
问题 Reading the documentation between Intel and AMD and looking at code makes it difficult at times to understand how to create a proper Task State Segment (TSS) that has no IO port bitmap (IOPB). There also seems to be confusion over creating a TSS with an IOPB as well since it seems ambiguous as to whether an IO Bitmap (IOPB) requires a trailing 0xff byte. I'm aware that there are is a dependency between the TSS and a TSS Descriptor (in the GDT). The TSS descriptor governs the base address of

How to install python2.6-devel package under CentOs 5

五迷三道 提交于 2019-11-30 08:38:56
问题 I need to install mysql-python under python2.6. mysql-python package needs python2.6-devel package that depends on the libpython2.6.so.1.0(64bit) I found on the net some python2.6-devel packages, but can't find libpython2.6 Server architecture is x86_64. Maybe someone have this lib, or know where i can find it. Thanks for help) 回答1: I have the same issue and this wonderful link solved it for me... http://blog.milford.io/2010/08/new-method-for-installing-python-2-6-4-with-mysql-python-on

C++ 64 bit int: pass by reference or pass by value

白昼怎懂夜的黑 提交于 2019-11-30 08:36:44
This is an efficiency question about 64 bit ints. Assuming I don't need to modify the value of a "int" parameter, should I pass it by value or reference. Assuming 32 bit machine: 1) 32 bit int: I guess the answer is "pass by value" as "pass by reference" will have overhead of extra memory lookup. 2) 64 bit int: If I pass by reference, I only pass 32 bit address on the stack, but need an extra memory lookup. So which one of them is better (reference or value)? What if the machine is 64 bit? regards, JP Pass by value - definitely. If the system is 64-bit it means it copies 64-bit word extremely

Can an x64 application use x86 assemblies - and vice versa?

放肆的年华 提交于 2019-11-30 07:46:26
问题 My application is built as a x64 application. After moving to VS2010 I got some problems which seems to be related to some x64/x86 mismatch in referenced dlls. Now I'm moving to target .NET4, and I get even more similar problems. My question is: What precautions do I need to take regarding mixing x64 and x86. Can it be done at all? I thought x64 applications should be able to use x86 dlls without problems. No? What about the other way? Can a x86 application reference an x64 dll - as long as

How MTRR registers implemented? [closed]

情到浓时终转凉″ 提交于 2019-11-30 07:37:21
x86/x86-64 exposes MTRR (Memory-type-range-register) that can be useful to designate different portions of physical address space for different usages (e.g., Cacheable, Unchangeable, Writecombining, etc.). My question is is anybody knows how these constrained on physical address space as defined by the MTRRs are enforced in hardware? On each memory access does the hardware check whether the physical address falls in a given range before the process decides whether it should look up the cache or lookup the writecombining buffer or send it to memory controller directly? Thanks Wikipedia says in